- Add new cvs code to cvs

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/model_f1x/Config.lb

@@ -0,0 +1,9 @@
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+driver model_f1x_init.o

src/cpu/intel/model_f1x/model_f1x_init.c

@@ -0,0 +1,55 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/chip.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+/* 256KB cache */
+static uint32_t microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+	
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_f1x_init(device_t dev)
+{
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+	x86_setup_mtrrs();
+	x86_mtrr_check();
+	
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_f1x_init,
+};
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f12 },
+	{ 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};

src/cpu/intel/model_f1x/multiplier.h

@@ -0,0 +1,55 @@
+
+/* 
+ ** NMI A20M IGNNE INTR
+ * X8  H H H H
+ * X9  H H H L projected
+ * X10 H H L H
+ * X11 H H L L
+ * X12 H L H H
+ * X13 H L H L
+ * X14 H L L H
+ * X15 H L L L 
+ * X16 L H H H
+ * X17 L H H L
+ * X18 L H L H
+ * X19 L H L L
+ * X20 L L H H
+ * X21 L L H L  projected
+ * X22 L L L H  projected
+ * X23 L L L L  projected
+ *
+ ** NMI INTR IGNNE A20M 
+ * X8  H H H H
+ * X9  H L H H projected
+ * X10 H H L H
+ * X11 H L L H
+ * X12 H H H L
+ * X13 H L H L
+ * X14 H H L L
+ * X15 H L L L 
+ * X16 L H H H
+ * X17 L L H H
+ * X18 L H L H
+ * X19 L L L H
+ * X20 L H H L
+ * X21 L L H L projected
+ * X22 L H L L projected
+ * X23 L L L L projected
+ */
+
+#define XEON_X8	 0xf
+#define XEON_X9  0xb  /* projected */
+#define XEON_X10 0xd
+#define XEON_X11 0x9
+#define XEON_X12 0xe
+#define XEON_X13 0xa
+#define XEON_X14 0xc
+#define XEON_X15 0x8
+#define XEON_X16 0x7
+#define XEON_X17 0x3
+#define XEON_X18 0x5
+#define XEON_X19 0x1
+#define XEON_X20 0x6
+#define XEON_X21 0x2  /* projected */
+#define XEON_X22 0x4  /* projected */
+#define XEON_X23 0x0  /* projected */