- Add new cvs code to cvs

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/x86/sse/disable_sse.inc

@@ -0,0 +1,18 @@
+	/*
+	 * Put the processor back into a reset state
+	 * with respect to the xmm registers.
+	 */
+	
+	xorps %xmm0, %xmm0
+	xorps %xmm1, %xmm1
+	xorps %xmm2, %xmm2
+	xorps %xmm3, %xmm3
+	xorps %xmm4, %xmm4
+	xorps %xmm5, %xmm5
+	xorps %xmm6, %xmm6
+	xorps %xmm7, %xmm7
+
+	/* Disable sse instructions */
+	movl	%cr4, %eax
+	andl	$~(3<<9), %eax
+	movl	%eax, %cr4

src/cpu/x86/sse/enable_sse.inc

@@ -0,0 +1,14 @@
+	/* preserve BIST in %eax */
+	movl %eax, %ebp
+
+	/*
+	 * Enable the use of the xmm registers
+	 */
+
+	/* Enable sse instructions */
+	movl	%cr4, %eax
+	orl	$(1<<9), %eax
+	movl	%eax, %cr4
+
+	movl	%ebp, %eax
+