Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@@ -22,6 +22,8 @@
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<li><a href="#Romstage">Romstage</a>
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<ol type="A">
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<li>Enable <a href="#SerialOutput">Serial Output"</a></li>
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<li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
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<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
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</ol>
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</li>
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</ol>
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@@ -328,6 +330,57 @@ Use the following steps to debug the call to TempRamInit:
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</ol>
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<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2>
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<p>
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The following steps implement the code to get the previous sleep state:
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</p>
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<ol>
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<li>Implement the fill_power_state routine which determines the previous sleep state</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x32:
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- Just after entering
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
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</li>
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<li>0x33 - Just after calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
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</li>
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<li>0x34:
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- Just after entering
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
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</li>
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</ol>
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</ol>
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<h2><a name="MemoryInit">MemoryInit Support</a></h2>
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<p>
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The following steps implement the code to support the FSP MemoryInit call:
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</p>
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<ol>
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<li>Add the chip.h header file to define the UPD values which get passed
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to MemoryInit. Skip the values containing SPD addresses and DRAM
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configuration data which is determined by the board.
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<p>
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<b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb
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file specifies the default values for these parameters. The build
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process creates the static.c module which contains the config data
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structure containing these values.
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</p>
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</li>
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<li>Edit romstage/romstage.c
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<ol type="A">
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<li>Implement the romstage/romstage.c/soc_memory_init_params routine to
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copy the values from the config structure into the UPD structure
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</li>
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<li>Implement the soc_display_memory_init_params routine to display
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the updated UPD parameters by calling fsp_display_upd_value
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</li>
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</ol>
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</li>
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</ol>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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