sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

remove erroneous cache disable.

Browse Source 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-06-14 13:56:28 +00:00
parent 73c92a4a7c
commit fd14d4414a
1 changed files with 11 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/cpu/amd/model_gx2/cpureginit.c
View File

@ -231,9 +231,13 @@ cpuRegInit (void){
wrmsr(msrnum, msr);
}
/* */
/* Cache Overides*/
/* */
#if 0
/* */
/* Cache Overides*/
/* */
/* This code disables the data cache. Don't execute this
* unless you're testing something.
*/
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@ -243,6 +247,9 @@ cpuRegInit (void){
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
wrmsr(msrnum, msr);
}
/* This code disables the instruction cache. Don't execute
* this unless you're testing something.
*/
/* Allow NVRam to override IM Setup*/
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
{
@ -251,6 +258,7 @@ cpuRegInit (void){
msr.lo |= IM_CONFIG_LOWER_ICD_SET;
wrmsr(msrnum, msr);
}
#endif
}