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soc/intel/apollolake: handle different memory profiles for apl and glk

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glk has different memory profile values than apl. Therefore, a
translation is required to correctly set the proper profile value
depending on what SoC (and therefore FSP) is being used. Based on
SOC_INTEL_GLK Kconfig value use different profiles.

BUG=b:74932341

Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25249
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aaron Durbin
2018-03-16 12:55:58 -06:00
parent a9f49366c0
commit fd228e979c
1 changed files with 72 additions and 19 deletions
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91
src/soc/intel/apollolake/meminit.c
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@@ -79,29 +79,82 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH; cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH;
} }
void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed) struct speed_mapping {
{ int logical;
uint8_t profile; int fsp_value;
};
switch (speed) { struct fsp_speed_profiles {
case LP4_SPEED_1600: const struct speed_mapping *mappings;
profile = 0x9; size_t num_mappings;
break; };
case LP4_SPEED_2133:
profile = 0xa; static const struct speed_mapping apl_mappings[] = {
break; { .logical = LP4_SPEED_1600, .fsp_value = 0x9 },
case LP4_SPEED_2400: { .logical = LP4_SPEED_2133, .fsp_value = 0xa },
profile = 0xb; { .logical = LP4_SPEED_2400, .fsp_value = 0xb },
break; };
default:
printk(BIOS_WARNING, "Invalid LPDDR4 speed: %d\n", speed); static const struct fsp_speed_profiles apl_profile = {
/* Set defaults. */ .mappings = apl_mappings,
speed = LP4_SPEED_1600; .num_mappings = ARRAY_SIZE(apl_mappings),
profile = 0x9; };
static const struct speed_mapping glk_mappings[] = {
{ .logical = LP4_SPEED_1600, .fsp_value = 0x4 },
{ .logical = LP4_SPEED_2133, .fsp_value = 0x6 },
{ .logical = LP4_SPEED_2400, .fsp_value = 0x7 },
};
static const struct fsp_speed_profiles glk_profile = {
.mappings = glk_mappings,
.num_mappings = ARRAY_SIZE(glk_mappings),
};
static const struct fsp_speed_profiles *get_fsp_profile(void)
{
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
return &glk_profile;
else
return &apl_profile;
}
static int validate_speed(int speed)
{
const struct fsp_speed_profiles *fsp_profile = get_fsp_profile();
size_t i;
for (i = 0; i < fsp_profile->num_mappings; i++) {
/* Mapping exists. */
if (fsp_profile->mappings[i].logical == speed)
return speed;
} }
printk(BIOS_WARNING, "Invalid LPDDR4 speed: %d\n", speed);
/* Default to slowest speed */
return LP4_SPEED_1600;
}
static int fsp_memory_profile(int speed)
{
const struct fsp_speed_profiles *fsp_profile = get_fsp_profile();
size_t i;
for (i = 0; i < fsp_profile->num_mappings; i++) {
if (fsp_profile->mappings[i].logical == speed)
return fsp_profile->mappings[i].fsp_value;
}
/* should never happen. */
return -1;
}
void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
{
speed = validate_speed(speed);
printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed); printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed);
cfg->Profile = profile; cfg->Profile = fsp_memory_profile(speed);
set_lpddr4_defaults(cfg); set_lpddr4_defaults(cfg);
} }