soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz

Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.

TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/fch.c

@@ -73,6 +73,14 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
+static void fch_clk_output_48Mhz(void)
+{
+	uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
+	/* Enable BP_X48M0 Clock Output */
+	ctrl |= BP_X48M0_OUTPUT_EN;
+	misc_write32(MISC_CLK_CNTL0, ctrl);
+}
+
 static void fch_init_acpi_ports(void)
 {
 	u32 reg;
@@ -172,6 +180,7 @@ void fch_init(void *chip_info)
 	acpi_clear_pm_gpe_status();
 
 	gpp_clk_setup();
+	fch_clk_output_48Mhz();
 }
 
 void fch_final(void *chip_info)

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -78,6 +78,8 @@
 #define   GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
 #define   GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
 
+#define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
+#define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
 #define MISC_I2C0_PAD_CTRL		0xd8
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0