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soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol

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Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with
the D3COLD_SUPPORT symbol, as it allows for more granular control.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Sean Rhodes
2023-02-27 13:08:50 +00:00
committed by Felix Held
parent fd51af6286
commit fd4ad29f18
10 changed files with 35 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/alderlake/Kconfig
View File

@ -328,12 +328,6 @@ config SOC_INTEL_I2C_DEV_MAX
int int
default 8 default 8
config SOC_INTEL_ALDERLAKE_S3
bool
default n
help
Select if using S3 instead of S0ix to disable D3Cold.
config ENABLE_SATA_TEST_MODE config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining" bool "Enable test mode for SATA margining"
default n default n

4
src/soc/intel/alderlake/acpi/tcss.asl
View File

@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
} }
} }
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0) Method (TCON, 0)
{ {
/* Reset IOM D3 cold bit if it is in D3 cold now. */ /* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0 STAT = 0
} }
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
/* /*
* TCSS xHCI device * TCSS xHCI device

12
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -28,16 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0) Method (_S0W, 0x0)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x04) Return (0x04)
#else #else
Return (0x03) Return (0x03)
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR0) Method (_PR0)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -49,12 +49,12 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -66,7 +66,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*

12
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR0) Method (_PR0)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -268,12 +268,12 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -285,7 +285,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*

8
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*
@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/ */
Name (SD3C, 0) Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Method (_PR0) Method (_PR0)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
@ -53,7 +53,7 @@ Method (_PR3)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
} }
#endif // SOC_INTEL_ALDERLAKE_S3 #endif // D3COLD_SUPPORT
/* /*
* XHCI controller _DSM method * XHCI controller _DSM method

6
src/soc/intel/tigerlake/Kconfig
View File

@ -206,12 +206,6 @@ config SOC_INTEL_I2C_DEV_MAX
int int
default 6 default 6
config SOC_INTEL_TIGERLAKE_S3
bool
default n
help
Select if using S3 instead of S0ix to disable D3Cold
config SOC_INTEL_UART_DEV_MAX config SOC_INTEL_UART_DEV_MAX
int int
default 3 default 3

4
src/soc/intel/tigerlake/acpi/tcss.asl
View File

@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
} }
} }
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0) Method (TCON, 0)
{ {
/* Reset IOM D3 cold bit if it is in D3 cold now. */ /* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
STAT = 0 STAT = 0
} }
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
/* /*
* TCSS xHCI device * TCSS xHCI device

12
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0) Method (_S0W, 0x0)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x04) Return (0x04)
#else #else
Return (0x03) Return (0x03)
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*
@ -40,7 +40,7 @@ Method (_S0W, 0x0)
*/ */
Method (_PR0) Method (_PR0)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -52,12 +52,12 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -69,7 +69,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*

10
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@ -247,7 +247,7 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
@ -256,7 +256,7 @@ Method (_S0W, 0x0, NotSerialized)
Method (_PR0) Method (_PR0)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -268,12 +268,12 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
@ -285,7 +285,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*

8
src/soc/intel/tigerlake/acpi/tcss_xhci.asl
View File

@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
} }
/* /*
@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/ */
Name (SD3C, 0) Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) #if CONFIG(D3COLD_SUPPORT)
Method (_PR0) Method (_PR0)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
@ -53,7 +53,7 @@ Method (_PR3)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
} }
#endif // SOC_INTEL_TIGERLAKE_S3 #endif // D3COLD_SUPPORT
/* /*
* XHCI controller _DSM method * XHCI controller _DSM method