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Drop CONFIG_WRITE_HIGH_TABLES

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It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
2013-02-27 23:45:20 +01:00
committed by Ronald G. Minnich
parent 9c29cfae8c
commit fd611f9c2c
38 changed files with 17 additions and 202 deletions
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7
src/northbridge/intel/i945/northbridge.c
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@@ -26,6 +26,7 @@
#include <device/hypertransport.h>
#include <stdlib.h>
#include <string.h>
#include <cbmem.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
#include "i945.h"
@@ -80,10 +81,6 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
@@ -173,11 +170,9 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
#endif
}
/* TODO We could determine how many PCIe busses we need in