From fd716f3457a44ae02b0a85d3b5e3a3d99117e868 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Thu, 3 Dec 2020 20:39:14 -0700
Subject: [PATCH] Casually disable TBT RTD3

Change-Id: Ia20aded6de9769d9e69a374e67b7ceb569169bc5
---
 src/soc/intel/tigerlake/acpi/tcss.asl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 98938339bf..a422458a7d 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -635,13 +635,13 @@ Scope (\_SB.PCI0)
 
 		Method (_ON, 0)
 		{
-			TG0N()
+			//TODO TG0N()
 		}
 
 		Method (_OFF, 0)
 		{
 			If (\_SB.PCI0.TDM0.SD3C == 0) {
-				TG0F()
+				//TODO TG0F()
 			}
 		}
 	}
@@ -655,13 +655,13 @@ Scope (\_SB.PCI0)
 
 		Method (_ON, 0)
 		{
-			TG1N()
+			//TODO TG1N()
 		}
 
 		Method (_OFF, 0)
 		{
 			If (\_SB.PCI0.TDM1.SD3C == 0) {
-				TG1F()
+				//TODO TG1F()
 			}
 		}
 	}
@@ -766,13 +766,13 @@ Scope (\_SB.PCI0)
 
 		Method (_ON, 0)
 		{
-			\_SB.PCI0.TCON()
+			//TODO \_SB.PCI0.TCON()
 			STAT = 1
 		}
 
 		Method (_OFF, 0)
 		{
-			\_SB.PCI0.TCOF()
+			//TODO \_SB.PCI0.TCOF()
 			STAT = 0
 		}
 	}