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soc/intel/braswell: add default option to use public FSP

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The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.

To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.

Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.

Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Matt DeVillier
2019-04-23 12:21:17 -05:00
committed by Nico Huber
parent 8c99a4859e
commit fd7440d231
12 changed files with 62 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/intel/braswell/chip.h
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@ -172,11 +172,6 @@ struct soc_intel_braswell_config {
UINT8 I2C4Frequency;
UINT8 I2C5Frequency;
UINT8 I2C6Frequency;
UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/
UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/
UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/
UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/
UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/
};
extern struct chip_operations soc_intel_braswell_ops;