diff --git a/src/mainboard/system76/galp5/bootblock.c b/src/mainboard/system76/galp5/bootblock.c
index 44489dfa6d..9b760b6e6e 100644
--- a/src/mainboard/system76/galp5/bootblock.c
+++ b/src/mainboard/system76/galp5/bootblock.c
@@ -7,5 +7,5 @@
 
 void bootblock_mainboard_init(void) {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-	dgpu_power_enable(1);
+	dgpu_power_enable(0);
 }
diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb
index 4ec2fccffa..83bb64ad0f 100644
--- a/src/mainboard/system76/galp5/devicetree.cb
+++ b/src/mainboard/system76/galp5/devicetree.cb
@@ -280,6 +280,10 @@ chip soc/intel/tigerlake
 			#TODO Disable ME and HECI
 			register "HeciEnabled" = "1"
 		end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci"
+		end
 		device ref pcie_rp5 on
 			# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
 			register "PcieRpEnable[4]" = "1"
diff --git a/src/mainboard/system76/galp5/gpio.h b/src/mainboard/system76/galp5/gpio.h
index 263db1face..b2f59ee8b0 100644
--- a/src/mainboard/system76/galp5/gpio.h
+++ b/src/mainboard/system76/galp5/gpio.h
@@ -14,6 +14,10 @@
 
 /* Pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
 		// DGPU_RST#_PCH
 		PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP),
 		// DGPU_PWR_EN
@@ -183,9 +187,9 @@ static const struct pad_config gpio_table[] = {
 		// PCH_I2C_SCL
 		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 		// UART2_RXD
-		PAD_NC(GPP_C20, NONE),
+		PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
 		// UART2_TXD
-		PAD_NC(GPP_C21, NONE),
+		PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
 		// LAN_PLT_RST#
 		PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
 		// PCH_GPP_C23 - 4.7k pull-down