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soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bits

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Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne
and Picasso makefiles.
This makes it impossible for platforms to change them.  This change puts
the hardcoded bits in Kconfig, allowing them to be modified by the
platform.

BUG=b:185514903
TEST=Verify that the correct Soft Fuse bits are set.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth
2021-04-16 11:36:01 -06:00
committed by Martin Roth
parent 564413246d
commit fdad5ad74b
4 changed files with 33 additions and 5 deletions
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11
src/soc/amd/picasso/Kconfig
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@@ -425,6 +425,17 @@ config PSP_VERSTAGE_SIGNING_TOKEN
help
Add psp_verstage signature token to the build & PSP Directory Table
config PSP_SOFTFUSE_BITS
string "PSP Soft Fuse bits to enable"
default "28"
help
Space separated list of Soft Fuse bits to enable.
Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
Bit 15: PSP post code destination: 0=LPC 1=eSPI
Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
See #55758 (NDA) for additional bit definitions.
endmenu
config VBOOT