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soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM size

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Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.

Update sabrina APOB DRAM size to match the fmap.

TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Fred Reitberger 2022-07-15 08:05:56 -04:00 committed by Felix Held
parent 0b4f49c792
commit fdb0758256
3 changed files with 7 additions and 4 deletions
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3
src/soc/amd/common/block/apob/apob_cache.c
View File

@ -23,6 +23,9 @@
#error Incorrect APOB configuration setting(s) #error Incorrect APOB configuration setting(s)
#endif #endif
_Static_assert(CONFIG_PSP_APOB_DRAM_SIZE == DEFAULT_MRC_CACHE_SIZE,
"APOB DRAM reserved space != to MRC CACHE size - check your config");
#define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ #define APOB_SIGNATURE 0x424F5041 /* 'APOB' */
/* APOB_BASE_HEADER from AGESA */ /* APOB_BASE_HEADER from AGESA */

4
src/soc/amd/sabrina/Kconfig
View File

@ -125,11 +125,11 @@ config PSP_APOB_DRAM_ADDRESS
config PSP_APOB_DRAM_SIZE config PSP_APOB_DRAM_SIZE
hex hex
default 0x20000 default 0x1E000
config PSP_SHAREDMEM_BASE config PSP_SHAREDMEM_BASE
hex hex
default 0x2021000 if VBOOT default 0x201F000 if VBOOT
default 0x0 default 0x0
help help
This variable defines the base address in DRAM memory where PSP copies This variable defines the base address in DRAM memory where PSP copies

4
src/soc/amd/sabrina/root_complex.c
View File

@ -76,7 +76,7 @@ struct dptc_input {
* | (C_ENV_BOOTBLOCK_SIZE) | * | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole | * | Unused hole |
* | (86KiB) | * | (30KiB) |
* +--------------------------------+ * +--------------------------------+
* | FMAP cache (FMAP_SIZE) | * | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
@ -88,7 +88,7 @@ struct dptc_input {
* | PSP shared (vboot workbuf) | * | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) | * | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE * +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (128KiB) | * | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack | * | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) | * | (EARLYRAM_BSP_STACK_SIZE) |