arm64: Remove cpu intialization through device-tree
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Furquan Shaikh
committed by
Julius Werner
Julius Werner
parent
b3f6ad3522
commit
fdb3a8d07d
@@ -131,7 +131,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
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ramstage-y += c_entry.c
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ramstage-y += stages.c
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ramstage-y += div0.c
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ramstage-y += cpu_ramstage.c
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ramstage-y += eabi_compat.c
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ramstage-y += boot.c
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ramstage-y += tables.c
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@@ -15,8 +15,11 @@
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <arch/lib_helpers.h>
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#include <arch/mmu.h>
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#include <arch/stages.h>
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#include <gic.h>
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#include "cpu-internal.h"
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void __attribute__((weak)) arm64_soc_init(void)
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@@ -42,10 +45,82 @@ static void seed_stack(void)
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*slot++ = 0xdeadbeefdeadbeefULL;
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}
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/* Set up default SCR values. */
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static void el3_init(void)
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{
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uint32_t scr;
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if (get_current_el() != EL3)
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return;
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scr = raw_read_scr_el3();
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/* Default to non-secure EL1 and EL0. */
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scr &= ~(SCR_NS_MASK);
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scr |= SCR_NS_ENABLE;
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/* Disable IRQ, FIQ, and external abort interrupt routing. */
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scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK);
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scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE;
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/* Enable HVC */
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scr &= ~(SCR_HVC_MASK);
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scr |= SCR_HVC_ENABLE;
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/* Disable SMC */
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scr &= ~(SCR_SMC_MASK);
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scr |= SCR_SMC_DISABLE;
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/* Disable secure instruction fetches. */
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scr &= ~(SCR_SIF_MASK);
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scr |= SCR_SIF_DISABLE;
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/* All lower exception levels 64-bit by default. */
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scr &= ~(SCR_RW_MASK);
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scr |= SCR_LOWER_AARCH64;
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/* Disable secure EL1 access to secure timer. */
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scr &= ~(SCR_ST_MASK);
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scr |= SCR_ST_DISABLE;
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/* Don't trap on WFE or WFI instructions. */
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scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK);
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scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE;
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raw_write_scr_el3(scr);
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isb();
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}
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void __attribute__((weak)) arm64_arch_timer_init(void)
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{
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/* Default weak implementation does nothing. */
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}
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static void arm64_init(void)
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{
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seed_stack();
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/* Set up default SCR values. */
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el3_init();
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/* Initialize the GIC. */
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gic_init();
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/*
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* Disable coprocessor traps to EL3:
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* TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR
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* and EL2/EL1 access to CPACR_EL1.
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* TTA [20] = 0, disable traps for trace register access from any EL.
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* TFP [10] = 0, disable traps for floating-point instructions from any
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* EL.
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*/
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raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
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CPTR_EL3_TFP_DISABLE);
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/*
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* Allow FPU accesses:
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* FPEN [21:20] = 3, disable traps for floating-point instructions from
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* EL0/EL1.
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* TTA [28] = 0, disable traps for trace register access from EL0/EL1.
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*/
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raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
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/* Arch Timer init: setup cntfrq per CPU */
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arm64_arch_timer_init();
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arm64_soc_init();
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main();
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}
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@@ -1,204 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <arch/lib_helpers.h>
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <gic.h>
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#include <timer.h>
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#include "cpu-internal.h"
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static struct cpu_info cpu_info;
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void __attribute__((weak)) arm64_arch_timer_init(void)
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{
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/* Default weak implementation does nothing. */
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}
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static inline void cpu_disable_dev(device_t dev)
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{
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dev->enabled = 0;
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}
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static struct cpu_driver *locate_cpu_driver(uint32_t midr)
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{
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struct cpu_driver *cur;
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for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) {
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const struct cpu_device_id *id_table = cur->id_table;
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for (; id_table->midr != CPU_ID_END; id_table++) {
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if (id_table->midr == midr)
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return cur;
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}
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}
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return NULL;
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}
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static int cpu_set_device_operations(device_t dev)
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{
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uint32_t midr;
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struct cpu_driver *driver;
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midr = raw_read_midr_el1();
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driver = locate_cpu_driver(midr);
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if (driver == NULL) {
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printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr);
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return -1;
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}
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dev->ops = driver->ops;
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return 0;
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}
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/* Set up default SCR values. */
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static void el3_init(void)
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{
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uint32_t scr;
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if (get_current_el() != EL3)
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return;
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scr = raw_read_scr_el3();
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/* Default to non-secure EL1 and EL0. */
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scr &= ~(SCR_NS_MASK);
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scr |= SCR_NS_ENABLE;
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/* Disable IRQ, FIQ, and external abort interrupt routing. */
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scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK);
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scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE;
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/* Enable HVC */
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scr &= ~(SCR_HVC_MASK);
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scr |= SCR_HVC_ENABLE;
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/* Disable SMC */
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scr &= ~(SCR_SMC_MASK);
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scr |= SCR_SMC_DISABLE;
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/* Disable secure instruction fetches. */
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scr &= ~(SCR_SIF_MASK);
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scr |= SCR_SIF_DISABLE;
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/* All lower exception levels 64-bit by default. */
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scr &= ~(SCR_RW_MASK);
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scr |= SCR_LOWER_AARCH64;
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/* Disable secure EL1 access to secure timer. */
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scr &= ~(SCR_ST_MASK);
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scr |= SCR_ST_DISABLE;
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/* Don't trap on WFE or WFI instructions. */
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scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK);
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scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE;
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raw_write_scr_el3(scr);
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isb();
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}
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static void init_this_cpu(void)
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{
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struct cpu_info *ci = &cpu_info;
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device_t dev = ci->cpu;
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cpu_set_device_operations(dev);
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printk(BIOS_DEBUG, "CPU%x: MPIDR: %llx\n", ci->id, ci->mpidr);
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/* Initialize the GIC. */
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gic_init();
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/*
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* Disable coprocessor traps to EL3:
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* TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR
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* and EL2/EL1 access to CPACR_EL1.
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* TTA [20] = 0, disable traps for trace register access from any EL.
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* TFP [10] = 0, disable traps for floating-point instructions from any
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* EL.
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*/
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raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
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CPTR_EL3_TFP_DISABLE);
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/*
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* Allow FPU accesses:
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* FPEN [21:20] = 3, disable traps for floating-point instructions from
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* EL0/EL1.
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* TTA [28] = 0, disable traps for trace register access from EL0/EL1.
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*/
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raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
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/* Arch Timer init: setup cntfrq per CPU */
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arm64_arch_timer_init();
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if (dev->ops != NULL && dev->ops->init != NULL) {
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dev->initialized = 1;
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printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
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dev->ops->init(dev);
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}
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}
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/* Fill in cpu_info structures according to device tree. */
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static void init_cpu_info(struct bus *bus)
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{
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device_t cur;
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for (cur = bus->children; cur != NULL; cur = cur->sibling) {
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struct cpu_info *ci;
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unsigned int id = cur->path.cpu.id;
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if (cur->path.type != DEVICE_PATH_CPU)
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continue;
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/* IDs are currently mapped 1:1 with logical CPU numbers. */
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if (id != 0) {
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printk(BIOS_WARNING,
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"CPU id %x too large. Disabling.\n", id);
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cpu_disable_dev(cur);
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continue;
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}
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ci = &cpu_info;
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if (ci->cpu != NULL) {
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printk(BIOS_WARNING,
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"Duplicate ID %x in device tree.\n", id);
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cpu_disable_dev(cur);
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}
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ci->cpu = cur;
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ci->id = cur->path.cpu.id;
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}
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}
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void arch_initialize_cpu(device_t cluster)
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{
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struct bus *bus;
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if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) {
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printk(BIOS_ERR,
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"CPU init failed. Device is not a CPU_CLUSTER: %s\n",
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dev_path(cluster));
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return;
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}
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bus = cluster->link_list;
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/* Check if no children under this device. */
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if (bus == NULL)
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return;
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el3_init();
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/* Initialize the cpu_info structures. */
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init_cpu_info(bus);
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/* Send it the init action. */
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init_this_cpu();
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}
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@@ -18,36 +18,6 @@
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#define asmlinkage
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#if !defined(__PRE_RAM__)
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#include <arch/barrier.h>
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#include <arch/mpidr.h>
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#include <device/device.h>
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enum {
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CPU_ID_END = 0x00000000,
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};
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struct cpu_device_id {
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uint32_t midr;
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};
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struct cpu_driver {
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/* This is excessive as init() is the only one called. */
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struct device_operations *ops;
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const struct cpu_device_id *id_table;
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};
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struct cpu_info {
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device_t cpu;
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unsigned int id;
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uint64_t mpidr;
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};
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/* Initialize CPU0 under the DEVICE_PATH_CPU_CLUSTER cluster. */
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void arch_initialize_cpu(device_t cluster);
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#endif /* !__PRE_RAM__ */
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static inline unsigned int smp_processor_id(void) { return 0; }
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/*
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@@ -63,4 +33,8 @@ void arm64_cpu_startup(void);
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*/
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void arm64_arch_timer_init(void);
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#if !defined(__PRE_RAM__)
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struct cpu_driver { };
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#endif
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#endif /* __ARCH_CPU_H__ */
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