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pistachio: implement clock setup for I2C0

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BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; I2C0 clock is
     set up properly.
BRANCH=none

Change-Id: I15ffc5f7d8e8aadfc3cd249284bc492d0d13d9a1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 6404ab6ad12ea1579eaf5ae55a9eddd9bd9f96e2
Original-Change-Id: Iafdf492291b47f0088f3b5e621d630b8d21ab106
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250450
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu
2015-02-17 18:28:34 +00:00
committed by Patrick Georgi
parent 7d16196a8e
commit fdce680759
2 changed files with 33 additions and 0 deletions
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32
src/soc/imgtec/pistachio/clocks.c
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@ -98,6 +98,12 @@
#define UART1CLKOUT_CTRL_ADDR 0xB8144240 #define UART1CLKOUT_CTRL_ADDR 0xB8144240
#define UART1CLKOUT_MASK 0x000003FF #define UART1CLKOUT_MASK 0x000003FF
/* Definitions for I2C0 setup */
#define I2C0CLKDIV1_CTRL_ADDR 0xB814413C
#define I2C0CLKDIV1_MASK 0x0000007F
#define I2C0CLKOUT_CTRL_ADDR 0xB8144140
#define I2C0CLKOUT_MASK 0x0000007F
/* Definitions for ROM clock setup */ /* Definitions for ROM clock setup */
#define ROMCLKOUT_CTRL_ADDR 0xB814490C #define ROMCLKOUT_CTRL_ADDR 0xB814490C
#define ROMCLKOUT_MASK 0x0000007F #define ROMCLKOUT_MASK 0x0000007F
@ -300,6 +306,32 @@ void uart1_clk_setup(u8 divider1, u16 divider2)
write32(UART1CLKOUT_CTRL_ADDR, reg); write32(UART1CLKOUT_CTRL_ADDR, reg);
} }
/*
* i2c_clk_setup: sets up clocks for I2C0
* divider1: 7-bit divider value
* divider2: 7-bit divider value
*/
void i2c0_clk_setup(u8 divider1, u16 divider2)
{
u32 reg;
/* Check input parameters */
assert(!(divider1 & ~(I2C0CLKDIV1_MASK)));
assert(!(divider2 & ~(I2C0CLKOUT_MASK)));
/* Set divider 1 */
reg = read32(I2C0CLKDIV1_CTRL_ADDR);
reg &= ~I2C0CLKDIV1_MASK;
reg |= divider1 & I2C0CLKDIV1_MASK;
write32(I2C0CLKDIV1_CTRL_ADDR, reg);
/* Set divider 2 */
reg = read32(I2C0CLKOUT_CTRL_ADDR);
reg &= ~I2C0CLKOUT_MASK;
reg |= divider2 & I2C0CLKOUT_MASK;
write32(I2C0CLKOUT_CTRL_ADDR, reg);
}
/* system_clk_setup: sets up the system (peripheral) clock */ /* system_clk_setup: sets up the system (peripheral) clock */
void system_clk_setup(u8 divider) void system_clk_setup(u8 divider)
{ {

1
src/soc/imgtec/pistachio/include/soc/clocks.h
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@ -28,6 +28,7 @@ int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
void system_clk_setup(u8 divider); void system_clk_setup(u8 divider);
void mips_clk_setup(u8 divider1, u8 divider2); void mips_clk_setup(u8 divider1, u8 divider2);
void uart1_clk_setup(u8 divider1, u16 divider2); void uart1_clk_setup(u8 divider1, u16 divider2);
void i2c0_clk_setup(u8 divider1, u16 divider2);
int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
void rom_clk_setup(u8 divider); void rom_clk_setup(u8 divider);
void eth_clk_setup(u8 mux, u8 divider); void eth_clk_setup(u8 mux, u8 divider);