Revert "mb/google/brya/var/vell: Remove unused i2c7 settings"

This reverts commit bd9cec8ae5.

Reason for revert: Enable i2c7 for amp changing to 2 channel
because vell setting amp on i2c0 and i2c7 on next phase

BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
     && checks EC log and ensures the DUT could enter s0ix.

Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/vell/gpio.c

@@ -57,10 +57,10 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
 	/* H7  : IC1_SCL ==> PCH_I2C_TPM_SCL */
 	PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
-	/* H12 : Reserved I2C7_SDAL for AMP */
+	/* H12 : I2C7_SDA ==> PCH_I2C_AUD_L_SDA */
-	PAD_NC(GPP_H12, NONE),
+	PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG),
-	/* H13 : Reserved I2C7_SCL for AMP */
+	/* H13 : I2C7_SCL ==> PCH_I2C_AUD_L_SCL */
-	PAD_NC(GPP_H13, NONE),
+	PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG),
 	/* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6),
 	/* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */

src/mainboard/google/brya/variants/vell/overridetree.cb

@@ -57,6 +57,15 @@ chip soc/intel/alderlake
 			.fall_time_ns = 400,
 			.data_hold_time_ns = 50,
 		},
+		.i2c[7] = {
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 45,
+				.scl_hcnt = 30,
+				.sda_hold = 20,
+			},
+		},
 	}"
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)"  # USB2_C3
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
@@ -78,7 +87,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C3] = PchSerialIoPci,
 		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C7] = PchSerialIoPci,
 	}"
 	device domain 0 on
 		device ref igpu on
@@ -353,6 +362,7 @@ chip soc/intel/alderlake
 				device i2c 15 on end
 			end
 		end
+		device ref i2c7 on end
 		device ref gspi1 on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""