soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions

Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.

Re-define in the common code.

Update coreboot code to use FSP_X_CONFIG consistently.

Tested=On OCP Delta Lake, boot up OS successfully.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>

Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/Makefile.inc

@@ -19,5 +19,6 @@ postcar-y += spi.c
 subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
+CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h
 
 endif ## XEON_SP_COMMON_BASE

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -16,8 +16,6 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp
 
-CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h
-
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b
 
 endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP

src/soc/intel/xeon_sp/cpx/romstage.c

@@ -154,7 +154,7 @@ static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required)
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	const struct device *dev;
 	const config_t *config = config_of_soc();
 

src/soc/intel/xeon_sp/cpx/upd_display.c

@@ -12,8 +12,8 @@ void soc_display_fspm_upd_params(
 	const FSPM_UPD *fspm_old_upd,
 	const FSPM_UPD *fspm_new_upd)
 {
-	const FSPM_CONFIG *new;
+	const FSP_M_CONFIG *new;
-	const FSPM_CONFIG *old;
+	const FSP_M_CONFIG *old;
 
 	old = &fspm_old_upd->FspmConfig;
 	new = &fspm_new_upd->FspmConfig;
@@ -31,8 +31,8 @@ void soc_display_fsps_upd_params(
 	const FSPS_UPD *fsps_old_upd,
 	const FSPS_UPD *fsps_new_upd)
 {
-	const FSPS_CONFIG *new;
+	const FSP_S_CONFIG *new;
-	const FSPS_CONFIG *old;
+	const FSP_S_CONFIG *old;
 
 	old = &fsps_old_upd->FspsConfig;
 	new = &fsps_new_upd->FspsConfig;

src/soc/intel/xeon_sp/include/soc/fsp_upd.h

@@ -3,7 +3,10 @@
 #ifndef _FSP_UPD_H_
 #define _FSP_UPD_H_
 
-/* Rename the FSP UPD structs to what they were historically called on other platforms. */
+/*
+ * Intel FSPs of XEON server platforms define FSPX_CONFIG
+ * instead of FSP_X_CONFIG, which is expected by coreboot.
+ */
 #define FSP_T_CONFIG FSPT_CONFIG
 #define FSP_M_CONFIG FSPM_CONFIG
 #define FSP_S_CONFIG FSPS_CONFIG

src/soc/intel/xeon_sp/skx/upd_display.c

@@ -32,8 +32,8 @@ void soc_display_fsps_upd_params(
 	const FSPS_UPD *fsps_old_upd,
 	const FSPS_UPD *fsps_new_upd)
 {
-	const FSPS_CONFIG *new;
+	const FSP_S_CONFIG *new;
-	const FSPS_CONFIG *old;
+	const FSP_S_CONFIG *old;
 
 	old = &fsps_old_upd->FspsConfig;
 	new = &fsps_new_upd->FspsConfig;

src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h

@@ -553,7 +553,7 @@ typedef struct {
 /** Offset 0x01E0
 **/
 	UINT8                     ReservedMemoryInitUpd[16];
-} FSP_M_CONFIG;
+} FSPM_CONFIG;
 
 /** Fsp M UPD Configuration
 **/