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soc/intel/common: Add PMC IPC commands for FIVR

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Add PMC IPC commands information for FIVR control functionality.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar
2021-08-31 21:14:52 +05:30
committed by Felix Held
parent 024b2bd2ed
commit fe2ac34d95
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
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@@ -16,6 +16,15 @@
#define PMC_IPC_CMD_SIZE_SHIFT 16
#define PMC_IPC_CMD_SIZE_MASK 0xff
/* IPC command to control FIVR Configuration */
#define PMC_IPC_CMD_COMMAND_FIVR 0xA3
/* IPC subcommand to write FIVR Register */
#define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
/* IPC subcommand to control RFI Control 0 register logic write */
#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00
/* IPC subcommand to control RFI Control 4 register logic write */
#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01
#define PMC_IPC_CMD_FIELD(name, val) \
((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT))