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intel/skylake: Clean up USB configuration in devicetree

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Instead of having many different arrays for USB configuration,
with each array containing one bit of information, have one
array containing all the information for each port.

This way we can put the basic tuning parameters into a
structure and then define structures for the basic supported
configurations.

The existing port definitions are taken from the Skylake HSIO
tuning guide.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados, verify USB functionality in
all ports.

Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506
Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/306734
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
2015-10-16 13:58:11 -07:00
committed by Patrick Georgi
parent 4f1fe47178
commit fe86666913
6 changed files with 226 additions and 153 deletions
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38
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@@ -53,35 +53,17 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "PortUsb20Enable[0]" = "1" # Type-C Port 1
register "PortUsb20Enable[1]" = "1" # Type-C Port 2
register "PortUsb20Enable[2]" = "1" # Bluetooth
register "PortUsb20Enable[4]" = "1" # Type-A Port (card)
register "PortUsb20Enable[6]" = "1" # Camera
register "PortUsb20Enable[8]" = "1" # Type-A Port (board)
register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card)
register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board)
#USB Per Port HS Preemphasis Bias
register "Usb2AfePetxiset" = "{0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}"
#USB Per Port HS Transmitter Bias
register "Usb2AfeTxiset" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
#USB Per Port HS Transmitter Emphasis
register "Usb2AfePredeemp" = "{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}"
#USB Per Port Half Bit Pre-emphasis
register "Usb2AfePehalfbit" = "{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
register "PortUsb30Enable[0]" = "1" # Type-C Port 1
register "PortUsb30Enable[1]" = "1" # Type-C Port 2
register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
#Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
register "Usb3HsioTxDeEmphEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
#USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
register "Usb3HsioTxDeEmph" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
#Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
register "Usb3HsioTxDownscaleAmpEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
#USB 3.0 TX Output Downscale Amplitude Adjustment
register "Usb3HsioTxDownscaleAmp" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \