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sb/intel/i82801gx: Add common LPC decode code

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Generic LPC decode ranges can now be set from the devicetree.

Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2019-11-09 14:19:04 +01:00
committed by Patrick Georgi
parent 675cb9152e
commit fecf77770b
43 changed files with 156 additions and 338 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/asus/p5gc-mx/devicetree.cb
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@@ -55,6 +55,9 @@ chip northbridge/intel/i945
register "p_cnt_throttling_supported" = "0"
# SuperIO Power Management Events
register "gen1_dec" = "0x00040291"
device pci 1b.0 on # High Definition Audio
ioapic_irq 2 INTA 0x10
end

16
src/mainboard/asus/p5gc-mx/romstage.c
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@@ -96,20 +96,6 @@ static u8 msr_get_fsb(void)
return fsbcfg;
}
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
// Enable COM1
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
| COMA_LPC_EN);
// Enable SuperIO Power Management Events
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291);
}
static void rcba_config(void)
{
/* Enable IOAPIC */
@@ -156,7 +142,7 @@ void mainboard_romstage_entry(void)
enable_lapic();
ich7_enable_lpc();
i82801gx_lpc_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

2
src/mainboard/asus/p5qpl-am/devicetree.cb
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@@ -45,6 +45,8 @@ chip northbridge/intel/x4x # Northbridge
register "ide_enable_primary" = "0x1"
register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1: PCIe x1 slot
device pci 1c.1 on # PCIe 2: NIC

15
src/mainboard/asus/p5qpl-am/romstage.c
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@@ -143,19 +143,6 @@ static void mb_lpc_setup(void)
ich7_setup_cir();
}
static void ich7_enable_lpc(void)
{
pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
/* Fixed IO decode ranges */
pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
/* LPC enable devices */
pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
| FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
/* IO decode range: HWM on 0x295 */
pci_write_config32(LPC_DEV, 0x84, 0x000295);
}
void mainboard_romstage_entry(void)
{
// ch0 ch1
@@ -164,7 +151,7 @@ void mainboard_romstage_entry(void)
u8 s3_resume;
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
i82801gx_lpc_setup();
mb_lpc_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);