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AGESA,binaryPI: Enable lapic early for udelay()

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Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Kyösti Mälkki
2019-12-15 21:37:38 +02:00
parent fa0df7d316
commit fedaac84da
4 changed files with 7 additions and 18 deletions
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6
src/cpu/amd/pi/00630F01/fixme.c
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@@ -85,10 +85,4 @@ void amd_initmmio(void)
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (CONFIG(UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
}

6
src/cpu/amd/pi/00660F01/fixme.c
View File

@@ -91,10 +91,4 @@ void amd_initmmio(void)
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
}

6
src/cpu/amd/pi/00730F01/fixme.c
View File

@@ -96,10 +96,4 @@ void amd_initmmio(void)
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
}