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AMD F14 southbridge update

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This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kerry She
2011-08-18 18:03:44 +08:00
committed by Stefan Reinauer
parent 16d3ec6a58
commit feed329a0c
65 changed files with 1301 additions and 983 deletions
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10
src/mainboard/advansus/a785e-i/mptable.c
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@@ -23,8 +23,8 @@
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
#include "pmio.h"
#include <cpu/amd/amdfam10_sysconf.h>
#include <SBPLATFORM.h>
extern int bus_isa;
extern u8 bus_rs780[11];
@@ -61,12 +61,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {