soc/intel/apollolake: Add support for LPSS I2C driver

Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver.  The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.

The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.

This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.

Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Kconfig

@@ -41,8 +41,9 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
 	select SMM_TSEG
 	select SOC_INTEL_COMMON
-	select SOC_INTEL_COMMON_SMI
 	select SOC_INTEL_COMMON_ACPI
+	select SOC_INTEL_COMMON_LPSS_I2C
+	select SOC_INTEL_COMMON_SMI
 	select SPI_FLASH
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
@@ -96,6 +97,11 @@ config CPU_ADDR_BITS
 	int
 	default 36
 
+config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
+	depends on SOC_INTEL_COMMON_LPSS_I2C
+	int
+	default 133
+
 config CONSOLE_UART_BASE_ADDRESS
 	depends on CONSOLE_SERIAL
 	hex "MMIO base address for UART"