soc/intel/apollolake: Add support for LPSS I2C driver

Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver.  The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.

The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.

This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.

Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/chip.h

@@ -18,7 +18,21 @@
 #ifndef _SOC_APOLLOLAKE_CHIP_H_
 #define _SOC_APOLLOLAKE_CHIP_H_
 
+#include <soc/gpio.h>
+#include <soc/intel/common/lpss_i2c.h>
+#include <device/i2c.h>
+
 #define CLKREQ_DISABLED		0xf
+#define APOLLOLAKE_I2C_DEV_MAX	8
+
+struct apollolake_i2c_config {
+	/* Bus should be enabled prior to ramstage with temporary base */
+	int early_init;
+	/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
+	enum i2c_speed speed;
+	/* Specific bus speed configuration */
+	struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
+};
 
 /* Serial IRQ control. SERIRQ_QUIET is the default (0). */
 enum serirq_mode {
@@ -79,6 +93,9 @@ struct soc_intel_apollolake_config {
 
 	/* Integrated Sensor Hub */
 	uint8_t integrated_sensor_hub_enable;
+
+	/* I2C bus configuration */
+	struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */