skylake: provide native gpio functionality

It's important to be able to configure the gpio pads at
various stages instead of a single place using FSP. Without
this support there is a lot of duplicated open-coded pad
configuration taking place both within the SoC code and
mainboards.

Current limitation is that all GPIOs are in ACPI mode. i.e.
The HostSW ownership register sets the pad configuration to
only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The
GPI_STS update is masked within the GPIO community registers.

BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289789
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11174
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/Kconfig

@@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
 	select COLLECT_TIMESTAMPS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_MICROCODE_IN_CBFS
+	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_HARD_RESET
 	select HAVE_MONOTONIC_TIMER