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Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something.

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Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
2009-05-02 00:50:58 +00:00
committed by Joseph Smith
parent 3544c6b3b0
commit fff297327d
2 changed files with 286 additions and 240 deletions
Download Patch File Download Diff File Expand all files Collapse all files

161
src/mainboard/rca/rm4100/gpio.c
View File

@@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net> * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -37,15 +37,9 @@ static void mb_gpio_init(void)
pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
/* Set GPIO25 to input and drive GPIO23 to high, /* Set GPIO23 to high, this enables the LAN controller. */
* this enables the LAN controller.
*/
udelay(10); udelay(10);
set_gpio = 0x0000ffff; set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
set_gpio |= 1 << 25;
outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
set_gpio = 0x1b3f0000;
set_gpio |= 1 << 23; set_gpio |= 1 << 23;
outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
@@ -53,68 +47,97 @@ static void mb_gpio_init(void)
dev = PME_DEV; dev = PME_DEV;
port = dev >> 8; port = dev >> 8;
outb(0x55, port); /* Enter the configuration state. */ /* Enter the configuration state. */
outb(0x55, port);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */ /* GP21 - LED_RED */
outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */ outl(0x01, PME_IO_BASE_ADDR + 0x2c);
outl(0x00, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */ /* GP30 - FAN2_TACH */
outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */ outl(0x05, PME_IO_BASE_ADDR + 0x33);
outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */ /* GP31 - FAN1_TACH */
outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */ outl(0x05, PME_IO_BASE_ADDR + 0x34);
outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */ /* GP32 - FAN2_CTRL */
outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */ outl(0x04, PME_IO_BASE_ADDR + 0x35);
outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */ /* GP33 - FAN1_CTRL */
outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */ outl(0x04, PME_IO_BASE_ADDR + 0x36);
outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */ /* GP34 - AUD_MUTE_OUT_R */
outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */ outl(0x00, PME_IO_BASE_ADDR + 0x37);
outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */ /* GP36 - KBRST */
outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */ outl(0x00, PME_IO_BASE_ADDR + 0x39);
outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
outl(0x00, PME_IO_BASE_ADDR + 0x35); /* GP32 */ /* GP37 - A20GATE */
outl(0x00, PME_IO_BASE_ADDR + 0x36); /* GP33 */ outl(0x00, PME_IO_BASE_ADDR + 0x3a);
outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */ /* GP42 - GPIO_PME_OUT */
outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */ outl(0x00, PME_IO_BASE_ADDR + 0x3d);
outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */ /* GP50 - SER2_RI */
outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */ outl(0x05, PME_IO_BASE_ADDR + 0x3f);
outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */ /* GP51 - SER2_DCD */
outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */ outl(0x05, PME_IO_BASE_ADDR + 0x40);
outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */ /* GP52 - SER2_RX */
outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */ outl(0x05, PME_IO_BASE_ADDR + 0x41);
outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */ /* GP53 - SER2_TX */
outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */ outl(0x04, PME_IO_BASE_ADDR + 0x42);
outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */ /* GP55 - SER2_RTS */
outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */ outl(0x04, PME_IO_BASE_ADDR + 0x44);
outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */ /* GP56 - SER2_CTS */
outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */ outl(0x05, PME_IO_BASE_ADDR + 0x45);
outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
outl(0x07, PME_IO_BASE_ADDR + 0x4f); /* GP5 */ /* GP57 - SER2_DTR */
outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */ outl(0x04, PME_IO_BASE_ADDR + 0x46);
outl(0x00, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
outl(0x00, PME_IO_BASE_ADDR + 0x57); /* FAN2 */ /* GP60 - LED_GREEN */
outl(0x50, PME_IO_BASE_ADDR + 0x58); /* Fan Control */ outl(0x01, PME_IO_BASE_ADDR + 0x47);
outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */ /* GP61 - LED_YELLOW */
outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */ outl(0x01, PME_IO_BASE_ADDR + 0x48);
outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */ /* GP3 */
outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */ outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
outb(0xaa, port); /* Exit the configuration state. */ /* GP4 */
outl(0x04, PME_IO_BASE_ADDR + 0x4e);
/* FAN1 */
outl(0x01, PME_IO_BASE_ADDR + 0x56);
/* FAN2 */
outl(0x01, PME_IO_BASE_ADDR + 0x57);
/* Fan Control */
outl(0x50, PME_IO_BASE_ADDR + 0x58);
/* Fan1 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x59);
/* Fan2 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x5a);
/* LED1 */
outl(0x00, PME_IO_BASE_ADDR + 0x5d);
/* LED2 */
outl(0x00, PME_IO_BASE_ADDR + 0x5e);
/* Keyboard Scan Code */
outl(0x00, PME_IO_BASE_ADDR + 0x5f);
/* Exit the configuration state. */
outb(0xaa, port);
} }

159
src/mainboard/thomson/ip1000/gpio.c
View File

@@ -37,15 +37,9 @@ static void mb_gpio_init(void)
pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
/* Set GPIO25 to input and drive GPIO23 to high, /* Set GPIO23 to high, this enables the LAN controller. */
* this enables the LAN controller.
*/
udelay(10); udelay(10);
set_gpio = 0x0000ffff; set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
set_gpio |= 1 << 25;
outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
set_gpio = 0x1b3f0000;
set_gpio |= 1 << 23; set_gpio |= 1 << 23;
outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
@@ -53,68 +47,97 @@ static void mb_gpio_init(void)
dev = PME_DEV; dev = PME_DEV;
port = dev >> 8; port = dev >> 8;
outb(0x55, port); /* Enter the configuration state. */ /* Enter the configuration state. */
outb(0x55, port);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */ /* GP21 - LED_RED */
outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */ outl(0x01, PME_IO_BASE_ADDR + 0x2c);
outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */ /* GP30 - FAN2_TACH */
outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */ outl(0x05, PME_IO_BASE_ADDR + 0x33);
outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */ /* GP31 - FAN1_TACH */
outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */ outl(0x05, PME_IO_BASE_ADDR + 0x34);
outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */ /* GP32 - FAN2_CTRL */
outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */ outl(0x04, PME_IO_BASE_ADDR + 0x35);
outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */ /* GP33 - FAN1_CTRL */
outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */ outl(0x04, PME_IO_BASE_ADDR + 0x36);
outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */ /* GP34 - AUD_MUTE_OUT_R */
outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */ outl(0x00, PME_IO_BASE_ADDR + 0x37);
outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */ /* GP36 - KBRST */
outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */ outl(0x00, PME_IO_BASE_ADDR + 0x39);
outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */ /* GP37 - A20GATE */
outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */ outl(0x00, PME_IO_BASE_ADDR + 0x3a);
outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */ /* GP42 - GPIO_PME_OUT */
outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */ outl(0x00, PME_IO_BASE_ADDR + 0x3d);
outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */ /* GP50 - SER2_RI */
outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */ outl(0x05, PME_IO_BASE_ADDR + 0x3f);
outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */ /* GP51 - SER2_DCD */
outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */ outl(0x05, PME_IO_BASE_ADDR + 0x40);
outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */ /* GP52 - SER2_RX */
outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */ outl(0x05, PME_IO_BASE_ADDR + 0x41);
outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */ /* GP53 - SER2_TX */
outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */ outl(0x04, PME_IO_BASE_ADDR + 0x42);
outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */ /* GP55 - SER2_RTS */
outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */ outl(0x04, PME_IO_BASE_ADDR + 0x44);
outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */ /* GP56 - SER2_CTS */
outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */ outl(0x05, PME_IO_BASE_ADDR + 0x45);
outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */ /* GP57 - SER2_DTR */
outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */ outl(0x04, PME_IO_BASE_ADDR + 0x46);
outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */ /* GP60 - LED_GREEN */
outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */ outl(0x01, PME_IO_BASE_ADDR + 0x47);
outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */ /* GP61 - LED_YELLOW */
outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */ outl(0x01, PME_IO_BASE_ADDR + 0x48);
outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */ /* GP3 */
outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */ outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
outb(0xaa, port); /* Exit the configuration state. */ /* GP4 */
outl(0x04, PME_IO_BASE_ADDR + 0x4e);
/* FAN1 */
outl(0x01, PME_IO_BASE_ADDR + 0x56);
/* FAN2 */
outl(0x01, PME_IO_BASE_ADDR + 0x57);
/* Fan Control */
outl(0x50, PME_IO_BASE_ADDR + 0x58);
/* Fan1 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x59);
/* Fan2 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x5a);
/* LED1 */
outl(0x00, PME_IO_BASE_ADDR + 0x5d);
/* LED2 */
outl(0x00, PME_IO_BASE_ADDR + 0x5e);
/* Keyboard Scan Code */
outl(0x00, PME_IO_BASE_ADDR + 0x5f);
/* Exit the configuration state. */
outb(0xaa, port);
} }