For some reason the "interface" for adding framebuffer information
is sitting in src/include/vbe.h while also guarding the call to
fill_lb_framebuffer() with vbe_mode_info_valid() along with some
macro if CONFIG_* for good measure.
Move the fill_lb_framebuffer() declaration to coreboot_tables.h and
provide a comment about how it should be used. Also, now that
there's no need for the notion of a global vbe_mode_info_valid()
remove it from the conditional call path of fill_lb_framebuffer().
Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
Change-Id: I1288871769014f4c4168da00952a1c563015de33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/19535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.
BUG=b:37687843
Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19452
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SD/MMC support is broken into several pieces. There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
and is defined in include/device/storage.h
The SD/MMC driver consists of several components:
* SDHCI controller code
* bouncebuf.c
* bouncebuf.h
* pci_sdhci.c
* sdhci.c
* sdhci.h
* sdhci_adma.c
* sdhci_display.c
* Flash storage device support
* mmc.c
* mmc.h
* sd.c
* sd_mmc.c
* sd_mmc.h
* storage.c
* storage.h
* storage_erase.c
* storage_write.c
Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.
Full read/write/erase operations are provided for those platforms which
want to take advantage. It is also possible to build the driver to
perform initialization only. By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.
After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
structures between bootblock through to romstage. This allows early
stages to preform the SD/MMC device initialization and later stages
to use the SD/MMC device without further initialization. The example
code initializes the SD/MMC device in bootblock and uses the SD/MMC
device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
may be passed from romstage to ramstage and eventually the payload.
The example uses the SD/MMC device in ramstage without further
initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib. The intent
is to pass the controller state to libpayload so that the SD/MMC
device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver
History:
Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:
* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup
TEST=Build and run on Reef and Galileo Gen2
Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The vendor.irq field was originally intended for use as the TPM 1.2
"command complete" interrupt. However, all actual coreboot tpm drivers
and hardware use the vendor.status method of checking command completion
instead, and this irq field is not used.
Let's just remove this unused functionality to simplify the code.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19396
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking
the reception of commands. Real IRQs are not supported in firmware,
however firmware can still poll interrupt status registers for the same
effect.
Commit 94cc485338 ("drivers/i2c/tpm/cr50: Support interrupts for status")
added support for the Cr50 driver on X86 platforms to use a KConfig file
to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is
not supplied, the Cr50 driver inserts a 20 ms wait.
Unfortunately this doesn't work so well when using the i2c connected Cr50
on ARM platforms. Luckily, a more generic implementation to allow a
mainboard to supply a Cr50 IRQ status polling function was solved for SPI
connected Cr50s by commit 19e3d335bd ("drivers/spi/tpm: using tpm irq to
sync tpm transaction").
Let's refactor the i2c c50 driver to use this same approach, and change
eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for
specifying the TPM flow control interrupt.
This essentially reverts these two commits:
48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status
And ports this commit to i2c/tpm/cr50:
19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction
As a side effect the tpm_vendor_specific IRQ field goes back to its
original usage as the "TPM 1.2 command complete" interrupt, instead of
being repurposed to hold the flow control IRQ.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19363
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM
is only on if we actually want to compile in the TPM code. For example,
in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't
depend on SPI_TPM.
This problem manifests itself as the following build issue when building
with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2":
src/Kconfig:296:error: recursive dependency detected!
src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50
src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50
src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM
src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2
src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2
MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Suggested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use spi_setup_slave to fill up the spi_slave structure with
pointer to spi_ctrlr structure which can then be used to perform all
spi operations.
Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add SSDT generator for MIPI CSI camera to create ACPI objects
used by the Intel kernel drivers.
* SSDB: Sensor specific database for camera sensor.
* PWDB: Power database for all the camera devices.
* CAMD: ACPI object to specify the camera device type.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated SSDT table
has the required entries.
Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18967
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
We're already reading the RTC whenever we file an event, we might as
well print out the value at that time. Having a few RTC timestamps in
the firmware log makes it easier to correlate that part of the log to a
particular boot once we start having multiple boots in the log.
Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.
BUG=b:36873582
Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19213
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used
with PC80_SYSTEM.
BUG=b:35583330
Change-Id: Ibe626a192d45cf2624368db42d369202a4003123
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19093
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Use proper CAR semantics for global/static variables.
2. Use spi_* functions directly instead of using a global structure to
store pointers to those functions.
BUG=b:36873582
Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The tis.c module is needlessly copying data to/from a 1260 byte
buffer on the stack. Each device's transport implementation (cr50.c
or tpm.c) maintains its own buffer, if needed, for framing purposes.
Therefore, remove the duplicated buffer.
BUG=b:36598499
Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19061
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The spi tis_sendrecv() implementation was always returning success
for all transactions. Correct this by returning -1 on error when
tpm2_process_command() returns 0 since that's its current failure
return code.
BUG=b:36598499
Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19058
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The tpm_info object is a global, but its symbol does not need to
be exposed to the world as its only used within tpm.c.
BUG=b:36598499
Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
In the case of start_transaction() failing the chip select is never
deasserted. Correct that by deasserting the chip select when
start_transaction() fails.
BUG=b:36598499
Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19056
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add support for using GPIO IRQ instead of PIRQ with an I2C device.
This allows a device to use an edge triggered interrupt that will
trigger on both high and low transitions.
The _DSD method for describing these GPIOs has a field for 'active
low' which is supposed to be 1 if the pin is active low, otherwise
is zero. The value in here doesn't mean too much for GpioInt() as
those will end up using the value from GpioInt() when it actually
requests the interrupt.
BUG=b:35581264
BRANCH=none
TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ
Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18835
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the
existing I2C TPM support. The Atmel part just passes the commands and
responses from the TIS layer across the I2C interface.
TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled
Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18800
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add debugging support for the TIS transactions for the I2C TPM chips.
TEST=Build and run on reef
Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following warnings detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for single statement blocks
WARNING: Unnecessary parentheses - maybe == should be = ?
WARNING: line over 80 characters
WARNING: missing space after return type
TEST=Build and run on Galileo Gen2
Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
