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system76-4.15
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3139 Commits

Author SHA1 Message Date
Li-Ta Lo
69085400f1 reformat 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-06 20:23:29 +00:00
Li-Ta Lo
5917c62749 more fix for vsm, not working yet 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-06 20:19:04 +00:00
Li-Ta Lo
8854d30d6e did I commit the last change? 
try to fix 0x10000026


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-03 22:20:05 +00:00
Yinghai Lu
9a791dffea new cache_as_ram support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-03 20:38:34 +00:00
Ronald G. Minnich
96cb656806 added this file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-22 16:25:49 +00:00
Ronald G. Minnich
7f809097f8 add vsm support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-21 15:24:46 +00:00
Ronald G. Minnich
e4ad801495 cpubug is fine. 
adding vsm support now.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-21 03:38:53 +00:00
Ronald G. Minnich
db44be9405 added definitions. added cpubug support. added object. Commented out 
msr set in northbridge that conflicted with the cpubug support. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-20 20:49:34 +00:00
Stefan Reinauer
3cb4dc9c6b small cleanup attempt in sc520 code. there needs to be some major spring 
cleaning


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-19 17:50:54 +00:00
Stefan Reinauer
dba3f846f0 - sc520 updates. move PAR setup to mainboard auto.c 
- some ts5300 code. Let's push this upstream for now.
- fix a typo in device.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-17 22:48:23 +00:00
Stefan Reinauer
410075e0f1 fix mmcrval, small cosmetics to raminit 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-03-17 18:32:10 +00:00
Li-Ta Lo
b2528aa653 remove unused GX1 asm code 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-02-28 16:30:41 +00:00
Li-Ta Lo
a51e6f1e56 more GX2 commit 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-02-27 18:28:30 +00:00
Ronald G. Minnich
f8a1228872 rename 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-01-28 19:55:01 +00:00
Ronald G. Minnich
2bb216a880 adding preliminary, and almost certainly wrong, rumba support. 
This is just a skeleton, basically, and will most likely not even 
compile yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-01-27 23:46:30 +00:00
Yinghai Lu
3a68aeb903 don't need copy_secondary_start_to_1m_below for non-smp 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-01-09 20:42:50 +00:00
Yinghai Lu
815ced3f7a 1M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-01-04 20:41:05 +00:00
Yinghai Lu
6c02eb2cb5 indirect jmp with * 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 23:13:13 +00:00
Yinghai Lu
30576601f6 from issue 53: don't set TOM2 if 4G less mem installed, opt for init_ecc 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 20:16:49 +00:00
Yinghai Lu
6f63c0297c support HDT disassembly when cache as ram auto stage 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 20:08:23 +00:00
Yinghai Lu
72ee9b0ebe issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1M 
support and pgtbl after 1M support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 02:39:33 +00:00
Yinghai Lu
f42e1770f9 make clear_1m_ram.c to support gcc 3 and gcc4 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-09 01:58:07 +00:00
Yinghai Lu
c3b3600222 use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-07 19:02:45 +00:00
Stefan Reinauer
7ce8c54e2b 1201_ht_bus0_dev0_fidvid_core.diff 
https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-02 21:52:30 +00:00
Stefan Reinauer
f5183cfa19 Applying YhLu's patch from issue 37. 
a. apic id liftting to way that kernel like and let bsp
   to stay with 0
b. hw memhole: solve if hole_startk == some node
   basek
                 
This, together with the previous one will break most of 
the tree, but Yinghai Lu is really good
at fixing things, so...

   


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-01 11:01:01 +00:00
Stefan Reinauer
806e146e75 Applying 11_26_car_tyan.diff from Yinghai Lu. 
NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-01 10:54:44 +00:00
Stefan Reinauer
f622d598db - Apply 11_24_a_s1_core.diff from 
https://openbios.org/roundup/linuxbios/issue24
- fix up for via epia-m



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-26 16:56:05 +00:00
Stefan Reinauer
af77a61a9c add another Via C3 cpu id reported by grzegorz@el-kom.pl 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-26 11:57:57 +00:00
Ronald G. Minnich
d6bd192f6c remove rev f ifdef 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 21:12:47 +00:00
Ronald G. Minnich
fb0a64ba77 CAR patch from YH LU 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 21:01:08 +00:00
Ronald G. Minnich
872141a402 Split out microcode updates. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 20:52:43 +00:00
Ronald G. Minnich
ed1f9a75b3 missed these. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 05:09:42 +00:00
Ronald G. Minnich
9b6b3d22a2 issue 25, various AMD patches 
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 04:56:36 +00:00
Ronald G. Minnich
9442591f42 fixed fsf address 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-22 16:47:40 +00:00
Ronald G. Minnich
43225bc804 EPIA-M fixup 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-22 00:07:02 +00:00
Ronald G. Minnich
86cbd33837 This was posted on issue tracker and approve by ron minnich 
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-21 23:22:21 +00:00
Stefan Reinauer
2fd467ce3c reverting rev 2082 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-03 08:13:39 +00:00
Eswar Nallusamy
ed00937103 ppc970 initial porting. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-02 17:32:49 +00:00
Jason Schildt
bc6281a8fe - See Issue Tracker id-6 "lnxi-patch-6-replacement" 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:28:41 +00:00
Jason Schildt
8b26cab08f - See Issue Tracker id-4 "lnxi-patch-4" 
- In addition:
	modified apic_id lifting to always lift all CPUs.  This may cause problems with older kernels.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:24:23 +00:00
Jason Schildt
6a2c09a386 - See Issue Tracker ID-3 "lnxi-patch3" 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:07:34 +00:00
Greg Watson
aa9ef4195a trying to compile... 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 21:55:47 +00:00
Greg Watson
5fc3aa73eb get include files right 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 20:32:05 +00:00
Greg Watson
58b971e799 start of 970 port 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 18:03:08 +00:00
Ronald G. Minnich
20d943d9f9 adding support for dell 1850 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 17:02:34 +00:00
Stefan Reinauer
6ab43fcc48 Updating FSF address in the code. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-05 18:17:45 +00:00
Ronald G. Minnich
803719a22d comments mods. THings are working better, so I'm less unhappy with 
this part :-)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-26 16:48:24 +00:00
Ronald G. Minnich
87888630b2 sc520 support -- ethernet works 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-23 17:08:58 +00:00
Jonathan McDowell
1718c4771b Make EPIA-M use CONFIG_TSC. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-14 16:33:10 +00:00
Steven J. Magnani
059182cc4f Print a failure message if a sibling CPU fails to start. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-14 13:52:06 +00:00