Since bert_errors_present() is only available when ACPI_BERT is selected
the ACPI table generation code needs to check that before calling the
function, so add bert_should_generate_acpi_table that returns false when
ACPI_BERT isn't selected or the return value of bert_errors_present()
when ACPI_BERT is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55024
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboards with variants may not always use the same cmos.layout file.
Turn the hardcoded path into a Kconfig symbol to allow changing it.
Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus
P8H61-M PRO produces an identical coreboot image.
Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CBFS mcache size default was eyeballed to what should be "hopefully
enough" for most users, but some recent Chrome OS devices have already
hit the limit. Since most current (and probably all future) x86 chipsets
likely have the CAR space to spare, let's just double the size default
for all supporting chipsets right now so that we hopefully won't run
into these issues again any time soon.
The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under
the assumption that Chrome OS images have historically always had a lot
more files in their RO CBFS than the RW (because l10n assets were only
in RO). Unfortunately, this has recently changed with the introduction
of updateable assets. While hopefully not that many boards will need
these, the whole idea is that you won't know whether you need them yet
at the time the RO image is frozen, and mcache layout parameters cannot
be changed in an RW update. So better to use the normal 50/50 split on
Chrome OS devices going forward so we are prepared for the eventuality
of needing RW assets again.
The RW percentage should really also be menuconfig-controllable, because
this is something the user may want to change on the fly depending on
their payload requirements. Move the option to the vboot Kconfigs
because it also kinda belongs there anyway and this makes it fit in
better in menuconfig. (I haven't made the mcache size
menuconfig-controllable because if anyone needs to increase this, they
can just override the default in the chipset Kconfig for everyone using
that chipset, under the assumption that all boards of that chipset have
the same amount of available CAR space and there's no reason not to use
up the available space. This seems more in line with how this would work
on non-x86 platforms that define this directly in their memlayout.ld.)
Also add explicit warnings to both options that they mustn't be changed
in an RW update to an older RO image.
BUG=b:187561710
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested on qemu/i440fx on X86_64:
- Page tables are found in cbfs (finding a file works)
- returns 0 when a file is not found
- works when there is no cbfs file at the start of the FMAP, e.g. with
the cbfs master header removed.
Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The slot ID can be passed in from the function caller but
parsing slot ID from devicetree is not yet supported and
would still be 0.
Add Slot ID in SMBIOS type 9 for Delta Lake.
Tested=Execute "dmidecode -t 9" to verify.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the prog_locate() step for stages and rmodules.
Instead, the stage and rmodule loading functions will now perform the
locate step directly together with the actual loading. The long-term
goal of this is to eliminate prog_locate() (and the rdev member in
struct prog that it fills) completely in order to make CBFS verification
code safer and its security guarantees easier to follow. prog_locate()
is the main remaining use case where a raw rdev of CBFS file data
"leaks" out of cbfs.c into other code, and that other code needs to
manually make sure that the contents of the rdev get verified during
loading. By eliminating this step and moving all code that directly
deals with file data into cbfs.c, we can concentrate the code that needs
to worry about file data hashing (and needs access to cbfs_private.h
APIs) into one file, making it easier to keep track of and reason about.
This patch is the first step of this move, later patches will do the
same for SELFs and other program types.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now smbios type 4 max speed field will use the maximum speed of
processor itself if CPUID value can be accessed. However, this field
should be the maximum processor speed supported by the system. Here
we use smbios_cpu_get_max_speed_mhz only to get correct value.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Extended Maximum Capacity field in SMBIOS type 16 so that
maximum dimm size can be over 2TB.
Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.
Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
