Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD. However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.
ACPI Error: AE_NOT_FOUND, While resolving a named reference package
element - \NULL (20200925/dspkginit-438)
Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.
Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.
Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).
Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes no practical problem, especially for coreboot where only
one process should access the SPI controller. It makes the code look
more spec compliant.
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
Software must initiate the next SPI transaction when this bit is 0.
Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.
BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
We print these out in the normal flow, so lets add them for S0i3 resume
as well.
BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This feature was never used. Let's remove it to keep things simple.
BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.
BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.
Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass
Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board
Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.
TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.
This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.
This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.
BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards
Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but
the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in
acpi/acpi.c, so define this option in arch/x86/Kconfig to have it
defined in all cases where the function that ends up using this
information gets called. Since we now have the type information for this
Kconfig option in a central place, it can be dropped from the Kconfig
file of the Intel southbridges that change the default value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using read32p to get the contents of the first 4 bytes of the HPET MMIO
region instead of a pointer dereference should clarify what's done in
that piece of code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable guybrush based platforms to send fuse spl command to PSP when
required.
BUG=b:180701885
TEST=On a platform that supports SPL fusing. Confirm that PSP indicates
fusing is required, and confirm coreboot sends command. Fusing is
required when the image is built with an SPL table requiring newer
minimum versions. A message indicating fusing was requested will appear
in the serial log. "PSP: Fuse SPL requested"
Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
