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48035 Commits

Author SHA1 Message Date
Eran Mitrani
311223ac38 mb/google/brya/var/brya: fix comment for I2C connections 
For brya, I2C1 is cr50, and I2C3 is Touchscreen

BUG=None
BRANCH=firmware-brya-14505.B
TEST=None

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-07-16 22:46:09 +00:00
Varshit B Pandya
d9bc689276 driver/wifi: Remove unused function wifi_emit_dsm 
As part of this CL https://review.coreboot.org/c/coreboot/+/61020
this function was decoupled and support for new DSM was added.
This function is no longer used so remove it.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Iad9dca8e50bad87178dfcc1951276703721d5f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-16 22:44:09 +00:00
Ritul Guru
c58f674411 soc/amd/picasso: Add MP2 I2C0 and I2C1 controller ACPI devices 
This change is to allow AMD MP2 I2C OS driver to access
I2C0/1 devices when MP2 firmware is loaded.

Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-16 22:43:07 +00:00
Christian Walter
106def9645 soc/intel/xeon_sp: Make gsi_bases platform independent 
This commit makes gsi_bases platform independent. It introduces two new
Kconfigs which set if there are IIO APICs on other devices than the PCH
or not, and where they do start.

Change-Id: I40db4a8fd90572757687f35bbd8eebd7229fc75a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65531
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-15 12:06:32 +00:00
Christian Walter
b1a4c62130 soc/intel/cannonlake: Update VR config for Coffee Lake 
This is based on the following Intel documents:
* 570805
* 570806
* 572062
* 571264

Change-Id: I199415902d26fa5341ef3212a9169836ea4df74a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-07-15 12:06:04 +00:00
Stanley Wu
cedaf72b8d mb/google/nissa/var/pujjo: Remove unsupport HDA device setting 
Pujjo only support RTL1019 amp device, remove MX98360A device setting

BUG=b:238716919
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-15 12:05:48 +00:00
Tim Wawrzynczak
17c77f5a86 mb/google/brya/var/agah: Disable ASPM for dGPU 
Since ASPM is not verified as fully functional yet, and the board is
still in development, this patch disables ASPM for the dGPU.

BUG=b:236676400
TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-07-15 12:05:07 +00:00
Mark Hsieh
69bf58d30e mb/google/nissa/var/joxer: Update Joxer config to latest schematic 
init overridetree.cb based on the latest schematic.

BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-07-14 23:13:15 +00:00
Sridahr Siricilla
096ce1444e soc/intel/alderlake: Support PCIe hardware compliance test mode 
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...

This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag

BUG=b:235863379
TEST=Compilation with and without the flag
     Verify code path with instrumentation

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-14 23:12:36 +00:00
Jeremy Compostella
1dc080fc1d soc/intel/common: Introduce SOC_INTEL_COMPLIANCE_TEST_MODE 
This config can be used to make coreboot configure the hardware to
meet compliance tests requirements. SoCs which support compliance
testing features should set the
SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag.

BUG=b:235863379
TEST=Successful compilation

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-14 23:12:14 +00:00
Johnny Li
188ed2b691 mb/google/volteer/eldrid:add new generic DDR4 SPDs for Eldrid 
Update DDR4 SPDs to Eldrid to include the following:

DRAM Part Name    ID to assign
H5AG36EXNDX019    0 (0000)

BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-14 23:11:39 +00:00
Arthur Heymans
efd2720e47 arch/x86: Mark prepare_and_run_postcar noreturn 
This moves the die() statement to a common place.

Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-07-14 23:10:30 +00:00
Arthur Heymans
84b2f9f5b8 lib/program_loaders.c: Mark run_ramstage with __noreturn 
This allows the compiler to optimize out code called after run_ramstage.

Also remove some die() statements in soc code as run_ramstage already
has a die_with_postcode statement.

Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-07-14 23:10:17 +00:00
Cliff Huang
b95a821576 mb/intel/adlrvp: remove I2S2 GPIO settings 
It turns out that there is no device connected to I2S2.
This patch clarifies the GPIO settings device association and remove
unnecessary configuration.

GPP_A8  -> default: GP-in ; set to NF1: SRCCLKREQ7#
GPP_A9  -> default: NF1: ESPI_CLK
GPP_A10 -> default: NF1: ESPI_RESET#

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
 2022-07-14 23:09:53 +00:00
Tim Crawford
59e03ebf4c mb/system76: TGL-U: Disable AER for CPU PCIe RP 
Disable PCIe Advanced Error Reporting on the CPU root port to prevent
some SSDs from timing out on S0ix suspend. AER results in the drive not
being able to switch from D3 back to D0.

    nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible)

Known to affect at least the following SSD models:

- ADATA XPG SX8200 Pro
- Samsung 970 EVO Plus (FW version: 2B7QCXE7)

Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-14 23:09:32 +00:00
Bill XIE
44ef2123b0 sb/intel/ibexpeak: Perform const correctness 
me_bios_path_values[] in me.c should not be mutable.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-07-14 23:09:09 +00:00
Bill XIE
ac136250b2 commonlib: Substitude macro "__unused" in compiler.h 
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.

However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.

Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-07-14 23:08:09 +00:00
Eric Lai
f7ba881f98 mb/google/brya/var/ghost4adl: Add EC_IN_RW_OD 
Follow latest schematic to add EC_IN_RW_OD.

BUG=b:238786599
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-07-14 21:28:10 +00:00
Eric Lai
f2c1d8f061 mb/google/brya/var/ghost4adl: Add SSD power sequence and remove weak 
Add SSD power sequence and remove the redundant weak.

BUG=b:238786597
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-07-14 21:28:00 +00:00
Jack Rosenthal
d8e5a28962 mb/google/brya/var/ghost4adl: Add module MT62F1G32D2DS-026 WT-B 
Add module MT62F1G32D2DS-026 WT:B and assign RAM code.

BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I811e1bbb985efe4198928f30ff6396a5b4368856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65796
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-14 21:27:45 +00:00
Petr Cvek
e75bb01efa northbridge/intel/i945: Fix GCC optimizing out cache preload jump 
Clock config setup must be run from cache. Original code used "goto"
to prefetch the code required to update the VCO (by jumping after
the code and back before). The GCC since at least 12.1.0 and clang
since at least 13.0.1 will elimitate these jumps.

Use inline assembler to force the original code flow.

TEST=Verified assembly code is the same as generated by GCC 12.1.0
and boot tested on Kontron 986LCD-M.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-07-14 12:51:12 +00:00
Yu-Ping Wu
f87489bbae soc/intel/broadwell: Drop vboot support 
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it
with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support
flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES),
drop vboot as well as ChromeOS support for all broadwell boards,
including auron, jecht and wtm2.

[1] https://issuetracker.google.com/issues/235293589

BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_GUADO -a
TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a

Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-07-14 12:50:40 +00:00
Arthur Heymans
a19bc34430 soc/amd/*: Move apm call out of MP init code 
This makes it easier to have common code for MP init on AMD systems.

Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-07-14 12:49:00 +00:00
Arthur Heymans
7f611018d4 soc/amd/fsp: Cache smm_region() results 
This avoids searching the HOB output multiple times when calling
smm_region().

Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-07-14 12:48:46 +00:00
Ren Kuo
6b3f7a9145 mb/google/brya/var/volmar: I2C timing fine tune 
Configure the I2C bus timing for all enabled I2C buses.

BUG=b:237751906
TEST=Verify the build for volmar board and measure the freq
     is under 400KHz

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Iffa128146f5d8bec6dd3d5c2d1e7efd96895dc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65604
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-14 12:46:59 +00:00
Franklin Lin
fd52e66e77 mb/google/brya/crota: Enable MAC address passthru support 
Enable the support for providing a MAC address
for a dock to use based on the VPD values set in the platform.

BUG=b:235045188
TEST=tested on Brya by setting VPD values and observing the string
returned by the AMAC() method:

> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"

> echo 1 > /sys/module/acpi/parameters/aml_debug_output
[acpi.aml_debug_output=1]
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"

Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I61b2a5e18bc17abeea0846f17e9be343e852c2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65603
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-14 12:46:44 +00:00
Stanley Wu
97b0cf774d mb/google/nissa/var/pujjo: Add WWAN power off sequence 
pujjo support FM101 WWAN, use wwan_power.asl to handle the 
power off sequence

BUG=b:238281124
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I53cd45c8030855c267d870d68d009c454350621e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-07-14 12:44:38 +00:00
Subrata Banik
21452e15bb mb/google/rex: Program EC ranges (host cmd and memory map) 
This patch adds chip config entries for EC host cmd and memory map
ranges.

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84a3b128a05c013d659e490a01198955ef383f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:43:25 +00:00
Subrata Banik
35c61216f4 mb/google/rex: Add chip config for USB devices 
+-------------+----------------+------------+
| USB 2.0     | Connector Type | OC Mapping |
+-------------+----------------+------------+
|      1      |       NC       |     NC     |
+-------------+----------------+------------+
|      2      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      3      |       NC       |     NC     |
+-------------+----------------+------------+
|      4      |     Type-C     |     NA     |
+-------------+----------------+------------+
|      5      |      WWAN      |     NA     |
+-------------+----------------+------------+
|      6      |     Camera     |     NA     |
+-------------+----------------+------------+
|      7      |       NC       |     NC     |
+-------------+----------------+------------+
|      8      |       DCI      |     NA     |
+-------------+----------------+------------+
|      9      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      10     |       BT       |     NA     |
+-------------+----------------+------------+

+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1     | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
|          1          |       Type-A      |    OC_3    |
+---------------------+-------------------+------------+
|          2          |        DCI        |     NA     |
+---------------------+-------------------+------------+

+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
|   1  |   Type C port 0   |    OC_0    |
+------+-------------------+------------+
|   3  |   Type C port 1   |     NA     |
+------+-------------------+------------+

BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iecab1318f683e3b53441cafe909bcfd978ee126b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-07-14 12:42:51 +00:00
Subrata Banik
9ffaf7f692 mb/google/rex: Add chip config for gspi devices 
+-----------+-------------+------------------+
| INTERFACE | PCI (B:D:F) | DEVICE           |
+-----------+-------------+------------------+
| GSPI-0    | 0:0x1e:2    | NA               |
+-----------+-------------+------------------+
| GSPI-1    | 0:0x1e:3    | Finger Print MCU |
+-----------+-------------+------------------+
| GSPI-2    | 0:0x12:6    | NA               |
+-----------+-------------+------------------+

BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b20e342cbca60821f82c07f72328cf63c0e5404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:42:19 +00:00
Subrata Banik
e54a8fd432 soc/intel/meteorlake: Add entry for GSPI2 device 
This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb.

Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value
to include GSPI2 as well.

BUG=b:224325352
TEST=Able to build and boot Google/Rex platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:41:50 +00:00
Subrata Banik
f9a179a66d mb/google/rex: Add chip config for UART devices 
This patch ensures LPSS UART 0 is used for the AP serial console as
per Rex Proto 0 schematics dated 07/05.

+-----------+-------------+-------------+
| INTERFACE | PCI (B:D:F) | DEVICE      |
+-----------+-------------+-------------+
| UART-0    | 0:0x1e:0    | For AP UART |
+-----------+-------------+-------------+
| UART-1    | 0:0x1e:1    | NA          |
+-----------+-------------+-------------+
| UART-2    | 0:0x19:2    | NA          |
+-----------+-------------+-------------+

BUG=b:224325352
TEST=Able to get AP UART over LPSS UART0 using emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:41:27 +00:00
Subrata Banik
691af099c8 mb/google/rex: Add chip config for I2C devices 
+-----------+--------------------+-------------+--------+
| INTERFACE | PCI Number (B:D:F) | DEVICE      | Speed  |
+-----------+--------------------+-------------+--------+
| LPSS I2C0 | 0:0x15:0           | WFC         | 400KHz |
|           |                    +-------------+--------+
|           |                    | AUDIO_DB    | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C1 | 0:0x15:1           | Touch Panel | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C2 | 0:0x15:2           | NC          | NC     |
+-----------+--------------------+-------------+--------+
| LPSS I2C3 | 0:0x15:3           | Touch Pad   | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C4 | 0:0x19:0           | TPM         | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C5 | 0:0x19:1           | UFC         | 400KHz |
|           |                    +-------------+--------+
|           |                    | SAR1        | 400KHz |
|           |                    +-------------+--------+
|           |                    | SAR2        | 400KHz |
|           |                    +-------------+--------+
|           |                    | HPS         | 400KHz |
+-----------+--------------------+-------------+--------+

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a28f175372542d441c787deb2a096382658ace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-07-14 12:40:52 +00:00
Subrata Banik
4c350eedbe mb/google/rex: Drop redundant cpu_cluster entry 
This patch drops redundant cpu_cluster definition from mainboard
specific devicetree.cb as soc chip config (chipset.cb) already
has the required entry.

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iad42985ead7269eaa739c31bede5948c2e25c67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:40:28 +00:00
Subrata Banik
f09586240b mb/google/rex: Add overridetree.cb for rex0 variant 
This patch adds initial PCI device entries into the override
devicetree.

BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16326747df46769f93813ce322ed8045449ffa85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:39:55 +00:00
Subrata Banik
0bf12acc72 mb/google/rex: Add initial devicetree.cb for rex baseboard 
This patch adds initial PCI device entries into the baseboard
devicetree.cb.

BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I944b03a6b3c9c592c09984dde483c855f1a2cd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-14 12:39:28 +00:00
Tim Wawrzynczak
bebdd4fb8a mb/google/brya/acpi: Fix GPIO assignment for GPIO_GPU_NVVDD_EN 
GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in
power.asl, but a double check of the schematic shows that the actual pad
is GPP_A17, so this patch fixes that.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-13 16:11:02 +00:00
Tim Wawrzynczak
21b187872e mb/google/brya/acpi: Remove NV_33 power rail from GC6 entry/exit sequences 
I misread my notes when writing the code for the GC6I/GC6O Methods, and
accidentally included NV_33 in the GC6 sequence, which is incorrect
(confirmed in the Hardware Design Guide). This patch removes the code
that brings NV_33 up and down during the GC6 sequences.

BUG=b:236676400
TEST=build

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-13 16:10:36 +00:00
Tim Wawrzynczak
52ccd293d7 mb/google/brya: Implement shutdown function for dGPU 
Variants of brya that have a dGPU also need to perform a special
shutdown sequence in the _PTS ACPI Method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib760fa65e6e021c0949187f13f038d3e952e5910
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-07-13 16:09:46 +00:00
Tim Wawrzynczak
ef886f3034 mb/google/brya/acpi/peg: Fix Power Resource _ON and _OFF 
The _ON and _OFF methods for the root port's power resource were
calling the _ON and _OFF in the PEGP namespace, which was the
incorrect method, it should have been NPON/NPOF, so this patch
updates that.

BUG=b:236676400

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-13 16:09:32 +00:00
Tim Wawrzynczak
5fefcd59a8 ec/google/chromec: Update ACPI handlers for GPU 
There is a new field in EC EMEM for arbitrary GPU data to be passed
from EC to ACPI FW; this patch adds support for it.

Also the current host event for _Q0C (EC_HOST_EVENT_USB_CHARGER) is
unused, and is being repurposed in the next CL, so this patch drops
the handler.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iff6f935a5bdc8c47277eaa6bcbedd5fc5ed311a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-13 16:09:06 +00:00
Tim Wawrzynczak
7c97e1255c mb/google/brya/acpi: Update GPIO polling method 
The preferred way of polling in ACPI I've seen is usually to just
divide the sleep into N chunks, and ignore the time taken in between.
This works in practice (validated with Timer calls before and after).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-13 16:08:56 +00:00
Tim Wawrzynczak
58f80bac47 mb/google/brya/acpi: Modify NBCI _DSM subfunction 
The NBCI "get callbacks" _DSM subfunction should utilize the same "get
callbacks" subfunction from the GPS _DSM subfunction; this patch adds
that Method call into the ACPI code.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-13 16:08:47 +00:00
Tim Wawrzynczak
ce29eab035 mb/google/brya/acpi: Keep track of dGPU power state 
To avoid extraneous calls from the kernel to _ON or _OFF, keep track
of the power state of the GPU in an integer and exit _ON and _OFF
routines early when attempting to enter the current state.

BUG=b:236676400

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-13 16:08:37 +00:00
Arthur Heymans
7ae8fa538e cpu/amd: Add common helpers for TSEG and SMM 
Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-07-13 14:56:38 +00:00
Michał Żygowski
b00ba8c247 mainboard/msi/ms7d25/gpio.h: Remove redundant NAF_VWE definition 
The NAF_VWE bit definition is already present in
src/soc/intel/common/block/include/intelblocks/gpio.h.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1fe713ee08438be49308f5e777cd466cdbc45d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2022-07-13 12:38:39 +00:00
Sean Rhodes
ebdc52df0d mb/starlabs/lite/{glk/glkr}: Remove Bluetooth USB port 
This reverts commit 0225af3c2b as
it has no effect as the USB interface is configured by FSP S.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2022-07-13 10:46:53 +00:00
Stanley Wu
56751735c1 mb/google/nissa/var/pujjo: Add WFC camera setting 
Modify USB2.0 port[6] setting for WFC camera support

BUG=b:235182560
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I78dad102be2d915a251f6528eef07f2056001b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65777
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-13 10:46:17 +00:00
Felix Held
207225c686 cpu/x86/mp_init: retype do_smm element in mp_state struct to bool 
The do_smm struct element in the mp_state struct was an int even though
it only had two possible states, so change it to bool to make this more
obvious. Also change the return type of is_smm_enabled from int to bool.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d2d95f0497649d67565243d14a5ab9c9cdda412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-07-13 10:44:08 +00:00
Tyler Wang
29ae26704c mb/google/nissa/var/craask: Move codec item to SSFC 
Move audio codec item from fw_config to SSFC.

BUG=b:238353613
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-07-13 10:43:52 +00:00