Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C
bus device structure. The internal I2C controllers are now handled by
the generic PCI driver approach and generic I2C access is enabled.
As orientation for the I2C code the actual solution from
soc/intel/apollolake I2C was taken. All the I2C specific parts were
removed from lpss.c and have been implemented in the I2C driver.
Future merge to soc/intel/common/block/i2c/i2c.c would be possible.
With this patch I2C chip devices can now be used in devicetree.
TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked.
Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To allow retraining memory without hotkey (for example in manufacturing
process), we want to enforce re-training when the recovery reason is set
to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running
"crossystem recovery_request=0xc4").
The special reason was created for X86 MRC cache, for ensuring RO
calibration data is filled (the underlying implementation was in vboot,
not coreboot); and on MT8183 we have only RW calibration, but it seems
totally fine to extend that for RW.
BRANCH=kukui
BUG=None
TEST=boots; crossystem recovery_reason=0xc4; reboot
Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.
Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.
BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui
Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.
This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous code actually set SlpS0WithGbeSupport even when GBE is
disabled in device tree and could cause power consumption in s0ix.
This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport,
PchPmSlpS0Vm075VSupport by device tree.
SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Commit 680027edf6 fixed a null dereference and logic bug in the tegra210
spi code:
soc/nvidia/tegra210: Fix potential NULL pointer dereference
Recent Coverity scan indicated potential NULL deference; if either
spi->dma_in or spi->dma_out are NULL, the fifo_error() check could
dereference a NULL pointer.
Also fixed what appears to be a logic bug for the spi->dma_out case,
where it was using the todo (count) from spi->dma_in.
Coverity is warning about the same problem for tegra124, so apply the
same fix there. Also, add braces around a while statement.
Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 124183, 124185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Autoport generates these structures as static so let's make it consistent.
This commit follows up on commit 6752b615 with Change-Id
I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for
const structures").
Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
This commit follows up on commit 9265f89f with Change-Id
I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid
HAVE_SMI_HANDLER conditional with smm-class").
Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I446cd267dec2b6c0f7742a6834c7ee950528ad5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Evaluated using 32-bit arithmetic, then used in a context that
expects an expression of type UINT64. Cast to UINT64 instead.
Change-Id: I4f0aa26e116b47505633897c790ca8e86ea5dc4e
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241847
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Rename the freeranges array to better match what they represent, i.e.
ranges that are used by the current running program and CAR region that
is not unallocated.
Skip adding the CAR region if cache-as-RAM is not active.
Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- drop FSP-1.1-only romstage.c and spd.c
TODO:
- testing
Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
