Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6.
If the ID does not match, the FSP USB will not set up the phy.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Cq-Depend: chrome-internal:4087511
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The update_efs_spi_speed allows changing the SPI speed manually in a
binary that has already been built. This will allow binaries not built
for the EM100 SPI ROM emulator to be updated so that they will work.
There is a corresponding change that will check to see if the EFS value
has been modified from the original speed and will prevent coreboot from
updating the SPI speed and mode.
BUG=b:177233017
TEST=Update SPI speed in existing binary. See that SPI speed has
changed.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I905a9fd8bd93a28aab927dffecbbcf24934b9e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, any chip with all its
settings will be silently dropped by sconfig if there is no device
node below it.
Let's adapt the parser to ensure that there is at least one `device`
entry. The intermediate `chipchildren_dev` rule applies until the
first `device` entry is found, then everything continues as before
with the `chipchildren` rule.
Change-Id: I54830bc1fc7d00a0605f3fe4d36a83ef57ef3312
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51119
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There was no code attached to this driver and hence one couldn't hook
it up to any device. Even if mentioned in the `devicetree.cb` it was
still dead code.
Change-Id: I12415ea9e0120b1d00524f8f39f9b2d02f46ba05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set GPIO GPP_A8 as high to enable EN_PP3300_TOUCHSCREEN.
also reduce enable delay time for meet panel power sequence.
BUG=b:197668845
BRANCH=volteer
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
Verify no corruption is seen on the screen
panel power sequence meet spec
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I9a0c1d0afafb2c446fcb3d18e1a67573218614e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57103
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to select the primary graphics device between the IGD and the
external PCIe GPU depending on the ONBOARD_VGA_IS_PRIMARY config.
The option sets the priority only. This means that if a high priority
is set for an external PCI device and it is not connected/not enabled,
then the device with a lower priority will be used, in our case it is
IGD.
TEST = Set PRIMARY_PCI and boot Linux on the Kontron mAL10 [1] with
the miniPCIe video adapter on the Silicon Motion SM750 controller. As
a result, the display connected to an external GPU device shows the
Tianocore logo + setup menu and the desktop.
[1] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.
BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
A chip entry in the devicetree is not hooked up without a device
beneath it. It seems the intention was to leave these superio
drivers unconfigured, so there should be no harm to turn the
entries into comments.
Change-Id: I6b606f35eba089b74c562084772d95be41cac39c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add Kconfig option TIANOCORE_ABOVE_4G_DECODE to pass build option to
edk2 to enable or disable "Above 4G Decode". Disabling allows certain Linux
distributions to boot such as Qubes, Zorin and Proxmox.
Requires commit `2f6d4cbcc7fa49462e607baed7626524ccd59ad3` that is
present in the `uefipayload_202107` branch of MrChromebox's edk2
repository.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3b1d15196c0ec611431af29031682fea626d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This aligns the GPIO MUX access more with the GPIO control register
access and will facilitate adding support for the remote GPIO bank. Also
change the GPIO number argument type to gpio_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the raw GPIO MMIO register access is now only used inside the
gpio_banks block, the gpio_read32 and gpio_write32 functions can be
moved to that block to reduce the visibility and enforce the usage of
the functions provided by the gpio_banks block.
The iomux_read8 and iomux_write8 functions can't be easily moved to the
gpio_banks block, since it's also used in the pre-SOC AMD chipsets that
use the ACPIMMIO access functions directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot.
BUG=b:198405404
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
copy config from guybrush reference board.
remove wwan & speaker amp due to the different solution is
used on nipperkin.
BUG=b:194031783
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I58a9b8393a965a9c793802d3e660829863b74375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The COMe module connector implements 8 GPIO lines from the CPLD/EC pins.
Use the Kempld GPIO driver[1] to configure these pins in accordance with
the COM Express Module Base Specification [2].
TEST = Set different logic states for the pin configured as outputs and
check them with an oscilloscope.
[1] CB:47595 , Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
[2] page 79-81, PICMG (R) COM.0 Revision 3.0 COM Express (R) Base
Specification - March 31, 2017.
Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54380
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
