Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.
Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Currently, BT offload is disabled/enabled unconditionally based on the
devicetree settings. BT offload uses I2S lines and cannot be enabled
when a I2S based audio daughter card is active. So we need to enable
BT offload only while using soundwire based audio daugther card.
BUG=b:175701262
TEST=Verified BT offload on brya with soundwire audio daughter card
BT offload enabled
Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
- The WWAN card was being disabled later than desired.
- The SD card was never being placed into reset on BoardID 1.
- Enable Touchscreen power
- Enable PCIe_RST1 at the same points as PCIe_RST
- Remove Redundant Bootblock settings
BUG=b:193036827
TEST=Build & Boot, look at GPIO states through boot process
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.
BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New binutils versions automatically resolve references to debug symbol
files and parse their content as well when objdump'ing data. This leads
to multiple mentions of symbols, so deduplicate references.
Change-Id: I5d597399c515904313ba36d7aab9178bc0dade14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set the bus master bit only if the global Kconfig switch
PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit
is needed for i210 because of some old OS drivers that do not set it
and won't work properly without it.
Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.
Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Chrome EC is relatively quick with retiring "old" boards from their
tree so when upreving it, the last veyron in that list that wasn't
commented out is gone as well.
Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the
upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in
the upcoming hardware build because SD7 support is dropped. Export the
EC_IN_RW GPIO for use by payload.
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the device can boot
successfully in both recovery and normal mode.
Cq-Depend: chromium:3043702
Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While the gcc(1) driver has the `-nostartfiles` option, ld(1), the
program the coreboot toolchain uses to link the object files, doesn't
have it.
In binutils before 2.36, this option is interpreted as `-n -o
startfiles`, in which the `-o` option is overridden by a later `-o`
option, so only the `-n` option has effect, which is the `--nmagic`
long option of ld(1). So the correct linker option in this place is
`--nmagic`.
It is tested that without `--nmagic`, ld can generate a much bigger
x86_64 romstage, so this option is still needed.
This error is found when trying to update binutils to 2.36 and later
versions, where ld(1) is unable to disambiguate options and reports an
error.
Change-Id: I27dc2209abdc6fec866716a252736c5cf236a347
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are in total three USB ports that are used on mc_ehl1:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
None of the ports supports overcurrent reporting.
Adjust the appropriate UPDs in devicetree to match the hardware
configuration.
Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without this configuration, even though there is no SD card it shows as
SD card is present and host controller waits for card to respond.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board with SD card and
without SD card, make sure if SD card not present then host controller
should not wait for card to respond.
Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.
Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This enables the MCAX checking and BERT entry generation for Cezanne.
TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
