This patch updates the GPIO lock configuration recommendation
kconfig string to ensure the SoC user can select the correct
config as applicable for the SoC.
Note: From MTL onwards GPIO lock config can be performed using
PCR write (MMIO write) and the GPIO team has confirmed this.
BUG=b:213596994
TEST=Able to fix below GPIO lock config error msg on MTL with
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled.
[INFO ] Locking pad configuration using SBI
[INFO ] gpio_pad_config_lock_using_sbi: Locking pad 73
configuration
[ERROR] SBI Failure: Transaction Status = 1
[ERROR] Failed to lock GPIO PAD, response = 1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Geralt reference design has both eMMC and SD card interfaces, so we have
to configure both in ramstage.
Implement msdc.c (mass storage device class) to place the eMMC and SD
card drivers.
This implementation is based on chapter 5.9 in MT8188 Functional
Specification.
TEST=boot to kernel using emmc successfully.
BUG=b:236331724
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to make 3 firmwares which differ only by Kconfig options and
can share a common variant directory.
ghost4adl: Board with an ADL chip.
ghost4es: Board near identical but has RPL-ES chip.
ghost: Will have final RPL silicon.
Since they will only differ by Kconfig options and Intel binary blobs,
let's not duplicate the variant directory but instead share it in
common.
BUG=b:239456576
BRANCH=firmware-brya-14505.B
TEST="make menuconfig", verify layout of board selection
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and
set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli.
BUG=b:218985167
TEST=emerge-brask coreboot and check RTL8111K LED behaviour
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
While adequate for ChromeOS, 16MiB VRAM is insufficient for current
mainline Linux and Windows amdgpu drivers to operate properly. Under
Linux, the driver fails to allocate a framebuffer and causes multiple
kernel panics. Under Windows, the driver fails to load due to
insufficient resources available. Revert the VRAM allocation to the
previous amount of 32MiB.
This change reverts
commit 87dcd0061a ("mainboard/google/kahlee: Reduce VRAM to 16MB")
Test: build/boot Linux 5.17.x on google/liara, verify framebuffer
allocation succeeds and no kernel panic reported.
Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b
Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The full dGPU power-on sequence, when executed from ACPI, is taking
roughly 15ms or so, which puts it close to the maximum of 20ms required
from the Nvidia spec. Changing the polling period to 100 us instead of 1
ms drastically reduces the time required for this sequence, now taking
typically 7 ms or so. This gives a lot more margin during the power on
sequence.
BUG=b:238466724
TEST=Sequence verified by EE on a scope
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Zoglin is like Hoglin, but with a smaller flash size, which requires
us to create a new variant.
BUG=b:239851866
BRANCH=None
TEST=Make sure BOARD_GOOGLE_ZOGLIN builds
Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change
sets it.
BUG=b:239628052
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot" and verify that the following configs
are set as:
CONFIG_BOARD_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB=32768
CONFIG_ROM_SIZE=0x02000000
Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PMIF, SPI, SPMI and PMIC init code.
These PMIC settings are used by MediaTek internally. We can find these
registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and
"MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek
designers.
TEST=build pass
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Ti50 hasn't implemented version reading yet. To avoid the confusing
error message
Did not recognize Cr50 version format
enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this
feature is not supported.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch moves the early GPIO programming from
`bootblock_mainboard_init` to `bootblock_mainboard_early_init`.
It will help to get the early debug prints as below.
TEST=Without this CL the initial report platform information
was missing as below:
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in
mcache @0xfef84d50
With this CL the complete bootblock serial msg is coming.
[NOTE ] coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022
bootblock starting (log level: 8)...
[DEBUG] CPU: Genuine Intel(R) 0000 @
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: f0270108
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d14 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id 7d55 (rev 00) is MeteorLake-P GT2
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0
in mcache @0xfef84d50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e092cd749359e54fe518de21671275af4b03062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The generic wifi driver currently contains a lot of intel specific
functionality that results in it not working properly on AMD platforms.
This commit updates the base device tree to use the generic PCIe driver
instead.
BUG=none
TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources
Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The generic wifi driver currently contains a lot of intel-specific
functionality that interferes with enabling wake-on-lan. This commit
changes the device tree to use the generic PCIe driver which better
supports this functionality.
BUG=b:237682766
TEST=Booted on skyrim device and verified that wake on LAN works
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes unneeded and unused functionality in the driver as part of
an effort to make the driver more generic and useful. The things that
have been removed are: `DmaProperty` and its associated `is_untrusted`
config, `_DSD` generation, and the companion device functionality. This
driver isn't currently used anywhere so there won't be any issues from
removing the above functionality.
BUG=b:237682766
TEST=Built and booted coreboot on Skyrim device
Change-Id: I0abd9148ab66ea9426069102ecc8c2fa77fea98e
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
