0fa92b31b0
src/cpu: add IS_ENABLED() around Kconfig symbol references
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Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf
Signed-off-by: Martin Roth <martinroth@google.com >
Reviewed-on: https://review.coreboot.org/20356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2017-07-13 23:55:25 +00:00
6add44bd3c
src/cpu/x86: Update/Add license headers to all files
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Change-Id: I436bf0e7db008ea78e29eaeef10bea101e6c8922
Signed-off-by: Martin Roth <martinroth@google.com >
Reviewed-on: https://review.coreboot.org/18405
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2017-02-22 22:23:11 +01:00
f7c55148c0
cpu: Trivial - drop trailing blank lines at EOF
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Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-on: http://review.coreboot.org/6207
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2014-07-08 13:52:43 +02:00
5a5c886b8d
SMP: Add arch-agnostic boot_cpu()
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We should not have x86 specific includes in lib/.
Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: http://review.coreboot.org/5156
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org >
Reviewed-by: Aaron Durbin <adurbin@google.com >
2014-02-11 21:55:30 +01:00
c66f1cbdae
Include boot_cpu.c for romstage builds
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ROMCC boards were left unmodified.
Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: http://review.coreboot.org/3853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de >
2013-08-15 20:49:03 +02:00
00093a81d3
Add an option to keep the ROM cached after romstage
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Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
Signed-off-by: Stefan Reinauer <reinauer@google.com >
Reviewed-on: http://review.coreboot.org/739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2012-03-30 01:07:49 +02:00
eafb18be43
Bootblock does not need a unique boot_cpu()
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Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.
Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.
Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de >
2011-12-05 12:20:43 +01:00
6ca7636c8f
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
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Creator: Yinghai Lu <yhlu@tyan.com >
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06 17:17:25 +00:00
fcd5ace00b
- Add new cvs code to cvs
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:29:29 +00:00
