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45853 Commits

Author SHA1 Message Date
Michał Żygowski
06cb997b0a soc/intel/apollolake: Move the PMC definitions to pmc.h file 
Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.

TEST=Build UP Squared and Intel GLKRVP sucessfully.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-08-24 12:59:48 +00:00
Yidi Lin
eb6642d8e4 soc/mediatek/mt8188: Remove GPT timer init 
GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.

BUG=b:229800119
TEST=boot to kernel

Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:55:41 +00:00
Won Chung
d597320d8e mb/google/brya/var/vell: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:19 +00:00
Won Chung
4eaa0a929f mb/google/brya/var/taniks: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:02 +00:00
Won Chung
020d43e553 mb/google/brya/var/taeko: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:50 +00:00
Won Chung
7f5c6d21c6 mb/google/brya/var/volmar: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:24 +00:00
Won Chung
d64da18c4a mb/google/brya/var/primus: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:53:08 +00:00
Won Chung
f860d5aba0 mb/google/brya/var/osiris: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:57 +00:00
Won Chung
fb69c56971 mb/google/brya/var/omnigul: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:33 +00:00
Won Chung
939d07ea35 mb/google/brya/var/mithrax: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:14 +00:00
Tyler Wang
34ce8c7377 mb/google/rex/var/karis: Disable GSPI0 
According to the schematic, karis does not have a SPI touchscreen,
remove related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-24 12:52:08 +00:00
Won Chung
d68bb7c84f mb/google/brya/var/marasov: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:52 +00:00
Won Chung
af1782cdcb mb/google/brya/var/kano: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:38 +00:00
Won Chung
1c8f5c7f1b mb/google/brya/var/gimble: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:51:25 +00:00
Won Chung
7e00d51c39 mb/google/brya/var/felwinter: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:55 +00:00
Won Chung
7fcdb9f902 mb/google/brya/var/crota: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:50:40 +00:00
Won Chung
767ff9127b mb/google/brya/var/banshee: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:21 +00:00
Martin Roth
59d5092454 soc/nvidia: Fix incorrect SPDX license 
The SPDX license header for this file did not match the license text
in the file.

Update the SPDX header and remove the license text.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:30:10 +00:00
Michael Strosche
8900323c4f soc/intel/jasperlake: Use boolean type where applicable 
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:15:18 +00:00
Anand Vaikar
1855cb4644 mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slots 
Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.


Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-08-23 16:09:00 +00:00
Naresh Solanki
40c740584b soc/intel/xeon/spr: Improve RMT configuration 
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed
for proper functioning when EnforcePopulationPor is set to 1.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 12:14:09 +00:00
Sen Chu
8cc8b3c14b soc/mediatek/mt8188: Simplify pmif init flow 
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx",
MT8188G used in ChromeOS project does not support clock hardware
monitor. Thus, we can simplify the initialization flow by removing the
hardware default value check.

BUG=b:292866009
TEST=emerge-geralt coreboot
BRANCH=none

Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2023-08-23 12:12:54 +00:00
Robert Chen
02295db726 mb/google/brya: Create quandiso variant 
Create the quandiso variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_QUANDISO

Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 12:08:34 +00:00
Tyler Wang
b951bdc156 mb/google/rex/var/karis: Remove WWAN temperature sensor 
According to the schematic, karis does not have a WWAN temperature
sensor, remove related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 07:38:05 +00:00
Daniel_Peng
3eed673659 mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-C 
This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.

BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
     And verified the USB2 eye diagram test result.

Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 07:36:35 +00:00
Morris Hsu
b6392ef4d7 mb/google/brask/var/constitution: Separate wifi sar table 
Separate constitution and intrepid wifi sar table in variant.c

BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage

Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 04:13:36 +00:00
Nick Vaccaro
eb08ae4ce1 mb/google/brya/var/bb/brask: enable HDMI gpios early 
Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.

BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.

Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-22 16:11:06 +00:00
Yu-Ping Wu
fae1eb3e66 soc/qualcomm: Add missing newlines for logs 
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-22 02:28:57 +00:00
Elyes Haouas
757509113b soc: Remove SOC_SPECIFIC_OPTIONS 
Move specific options under the boolean and remove dummy
SOC_SPECIFIC_OPTIONS.

Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-21 23:45:43 +00:00
Tyler Wang
b85e305961 mb/google/rex/var/karis: Remove world facing camera 
According to the schematic, karis does not have a WFC.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-21 23:31:47 +00:00
Matt DeVillier
e956379a19 ec/google/wilco/superio: Adjust PS2K HID/CID for Windows drivers 
Allows coolstar's Windows overlay drivers to attach, while not affecting
operation under Linux or ChromeOS

TEST=build/boot Win11, Linux 6.x on google/drallion

Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 23:20:06 +00:00
CoolStar
9c80cb81aa ec/google/wilco/acpi: Read message when notifying UCSI 
Allows the EC to be properly notified of type-c events like charger
wattage too low (eg),

TEST=build/boot Win11, Linux 6.x on google/drallion

Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 23:19:18 +00:00
CoolStar
4a587b8e96 ec/google/wilco: Correct scope of UCSI ACPI device 
Set the USCI device scope to _SB and set HID to USBC000 so Windows
driver attaches. This matches the ACPI used by the non-Chromebook
version of the Dell Latittude 7410 (which uses the same EC).

TEST=build/boot Win11 on google/drallion

Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 23:17:59 +00:00
Matt DeVillier
23c718c93a ec/google/wilco/acpi: Unhide GOOG000C ACPI device 
Allows coolstar's Windows drivers to attach.

TEST=build/boot Win11 on google/drallion

Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-21 23:16:50 +00:00
Matt DeVillier
010dd4c8f0 ec/google/wilco/acpi/dptf: Fix mutex synclevel 
Both Windows and MacOS get cranky if the Mutex synclevel is non-zero,
aborting any Acquire() call with Mutex param that has a non-zero
synclevel.

TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and
functional.

Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 23:16:24 +00:00
Tim Crawford
a129f8f2fe soc/intel/alderlake: add GPIO definitions for RPL PCH 
The RPL PCH uses a different ACPI Device ID than ADL PCH.

Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-21 23:10:38 +00:00
Michał Żygowski
c25f00acfa mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI) 
TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core
i5-13600K using UEFI Payload.

Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-21 21:21:08 +00:00
Michał Żygowski
c651a27b53 vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOT 
Similar situation happened last year when IoT FSP for ADL-S came out
before the Client FSP variant: https://github.com/intel/FSP/issues/83
It seems IoT FSP publishes the MemInfoHob.h file much later due to
legal reasons. Hack the missing file to get the builds using RPL-S IoT
FSP from repo working properly.

This change could be merged, subject for later revert (when the header
file is published).

Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-21 21:17:04 +00:00
Michał Żygowski
12a1fc2939 soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSP 
PchPcieClockGating and PchPciePowerGating UPDs are not yet available
in RPL-S IOT FSP. It also looks like those UPDs are not generally
available in all public RaptorLake FSP headers yet, so guard it
against SOC_INTEL_RAPTORLAKE to avoid build errors.

Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2023-08-21 21:16:53 +00:00
Elyes Haouas
6f063d97a6 soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONS 
Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 18:18:29 +00:00
Matt DeVillier
f0f0f9ad9c mb/google/skyrim/var/crystaldrift: drop commented out line in DT 
Line is a duplicate, commented out. Drop it as it serves no purpose.

Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-21 14:43:49 +00:00
Krystian Hebel
d3909e1793 device/dram: add DDR4 RCD I2C access functions 
Registering Clock Driver (RCD) is responsible for driving address and
control nets on RDIMM and LRDIMM applications. Its operation is
configurable by a set of Register Control Words (RCWs). There are two
ways of accessing RCWs: in-band on the memory channel as MRS commands
("MR7") or through I2C.

Access through I2C is generic, while MRS commands are passed to memory
controller registers in an implementation-specific way.

See JESD82-31 JEDEC standard for full details.

Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-21 14:43:08 +00:00
Michael Strosche
757e0c1d40 soc/intel/apollolake/chip.h: Use boolean type where applicable 
Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-21 14:31:46 +00:00
Arthur Heymans
db766c702a cpu/x86/smm: Don't save EFER 
The EFER MSR is in the SMM save state and RSM properly restores it.
Returning to 32bit mode was only done so that fxsave was done in the
same mode as fxrstor, but this is no longer done.

See commit 1efca4d570 (cpu/x86/smm: Drop fxsave/fxrstor logic)

TESTED on qemu: the smihandler works fine.

Change-Id: Ie0e9584afd1f08f51ca57da5c4350042699f130d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-21 12:14:25 +00:00
Krystian Hebel
6603605d75 device/dram: add DDR4 MRS commands 
Change-Id: I9d4f048c859bc89897d50a5a07468c3375aa1dcf
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-21 12:07:01 +00:00
Kilari Raasi
01f4f5db94 vc/intel/fsp/mtl: Add PsysPmax FspmUpd 
This patch adds the PsysPmax Upd to FSPM header file.

FSPM:
1. Add 'PsysPmax' UPD
2. Address offset changes

BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-21 09:34:07 +00:00
Elyes Haouas
ad867f385c meteorlake/include/soc/iomap: Remove unused HPET_BASE_ADDRESS 
Remove unused HPET_BASE_ADDRESS.
It is already defined at <arch/hpet.h>.

Change-Id: I8c517283e56915873b8e1798571642fd9d8a5764
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
 2023-08-21 08:16:45 +00:00
Elyes Haouas
d14f0a04f4 soc/samsung/exynos5250/clock: Remove space before semicolon 
Change-Id: Id0adfd0e25806aef836f75e83ff86a55a5d799d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-20 22:00:03 +00:00
Elyes Haouas
ece3bf37f9 soc/intel/bdw/pch: Remove SOC_INTEL_BROADWELL conditional 
broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So
remove 'if SOC_INTEL_BROADWELL' condition and duplicated
'INTEL_LYNXPOINT_LP'

Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-20 18:44:10 +00:00
Matt DeVillier
0ace876a74 ec/google/wilco: Fix ACPI EC RAM read/write ops 
While debugging lack of battery status under Windows, it was discovered
that the read/write flags in the args to the EC RAM 'ECRW' method were
not being correctly identified. Force set them from the R() and W()
methods which call ECRW() so those calls are processed properly.

TEST=build/boot Windows on google/drallion, verify battery status,
charging, etc are all reported properly.

Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf
Signed-off-by: Coolstar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-20 18:28:48 +00:00