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45853 Commits

Author SHA1 Message Date
Subrata Banik
247dd0e131 soc/intel/meteorlake: Enable GPIO IOSTANDBY configuration 
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.

TEST=Able to build and boot google/rex. GPIO debug print is showing
GPIO PAD config DW1 bit[14:17] are getting programmed.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-20 15:50:47 +00:00
Jason Glenesk
60875b4718 soc/amd/mendocino: Consume fsp misc_data hob 
Provide support function to query fsp misc_data hob and return smu
reported power and thermal limit.

BUG=b:253301653
TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in
the hob.

Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-20 01:33:20 +00:00
Ivy Jian
665c58b77a mb/google/rex: Enable USB camera power 
Add enable_gpio for USB power resource

BUG=b:273891168
TEST=Able to detect USB CAM

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I08ebe560c8b75c8b590c889b7b90dbe678318d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-20 01:23:30 +00:00
EricKY Cheng
fc484bf2ae mb/google/skyrim/var/winterhold: Update DPTC settings for final version 
Follow thermal team's request on b/248086651 comment#32. Update the
thermal table setting for each mode and the conditions of temperature
switching.

BUG=b:248086651,b:241180483
TEST=emerge-skyrim coreboot

Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
 2023-03-20 01:20:57 +00:00
Tim Chu
84fe84da84 soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SP 
Intel SPR-SP chipset has EBG instead of LBG.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-19 09:53:41 +00:00
Jonathan Zhang
3ed903fda9 soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code 
It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.

Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2023-03-19 09:53:02 +00:00
Jonathan Zhang
15fc45982b soc/intel/xeon_sp/spr: Add header files and romstage code 
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.

Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2023-03-19 09:49:03 +00:00
Subrata Banik
ecb4a24eaa soc/intel/mtl: Choose serial msg log_level based on DIMM count 
This patch modifies the serial msg log_level at runtime to highlight
an ERROR if the DIMM count is zero. It would help to draw the
attention while parsing the serial msg and catch any underlying issue.

TEST=Able to see ERROR msg while booting google/rex with FSP v3064

Without this patch:
    [DEBUG]  0 DIMMs found

With this patch:
    [ERROR]  No DIMMs found

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-19 07:17:23 +00:00
Eric Lai
7877ceda9e mb/google/rex: Move BOARD_GOOGLE_BASEBOARD_REX to Kconfig.name 
Align project style with other chrome projects.

TEST=built FW not changed

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icfd1d274216d387cab6feb68afa49fc63c8c52e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-19 05:12:36 +00:00
Eric Lai
58efd60175 mb/google/rex: Add DRIVERS_GENESYSLOGIC_GL9755 
Rex uses GL9755 and miss select the driver.

BUG=b:273906526
TEST=SD card is functional.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I674b052689c80873e8a3b295d15788f3a93f0b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-19 05:12:23 +00:00
David Hendricks
97117dbace soc/intel/xeon_sp: add MSR definitions for SPR-SP 
Some MSRs used in SPR code are common among currently supported
Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs
which have changed are added to SPR's soc_msr.h.

Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
 2023-03-19 00:54:05 +00:00
Jonathan Zhang
b77ea4c54a soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headers 
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
 2023-03-19 00:53:06 +00:00
Jonathan Zhang
b94cc7d367 soc/intel/xeon_sp: Add P2SB definition for SPR-SP 
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2023-03-19 00:51:46 +00:00
Michael Büchler
41ed2cb20e mb/asrock/h77pro4-m: Use VBT provided by Linux' debugfs 
The current VBT causes problems with Windows 10. Once the Intel driver
is used instead of the generic graphics driver, the display turns off
although the system keeps running normally. Linux has no issues. It had
been extracted from the vendor video BIOS, which in turn had been
extracted from the vendor firmware.

This change replaces the VBT with one that was dumped through debugfs
and the drm/i915 driver in Linux, booted from the vendor firmware at
version 2.10 (beta). It fixes the issue with the Intel graphics driver
on Windows 10.

Change-Id: Icbb3950b37dad5ed308f3bafb73b71859227d26b
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73711
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-18 11:06:11 +00:00
Michał Żygowski
c7fee24887 soc/intel/alderlake: Hook the VT-d DMA protection option 
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-17 13:54:34 +00:00
Michał Żygowski
a49945e4b7 soc/intel/alderlake/hsphy.c: Handle case with DMA protection 
The HSPHY firmware must be downloaded to DMA-allowed host address
space. Check for DMA buffer presence and use it as the buffer for HSPHY
firmware to be downloaded from CSME.

TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4
with DMA protection enabled.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-17 13:54:09 +00:00
Michał Żygowski
5f05ee2a0a soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTD 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-17 13:53:59 +00:00
Michał Żygowski
e6225874eb intelblocks/vtd: Add VT-d block with DMA protection API 
Add new common block with VT-d/IOMMU support. The patch adds an
option to enable DMA protection with PMR. However the payload and
OS must support VT-d in order to properly handle I/O devices.

TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
 2023-03-17 13:53:53 +00:00
Subrata Banik
9a035ede17 vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064 
This patch updates the Memory Hob Info data structure as per FSP
v3064 source code change.

BUG=b:273894357
TEST=Able to see `smbios type 17` table while booting google/rex.

Without this patch:
    [DEBUG] 0 DIMM found

With this patch:
    [DEBUG] 8 DIMM found

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-03-17 07:44:07 +00:00
van_chen
0533867a08 mb/google/nissa/var/uldren: Create RAM ID table 
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
K3KL6L60GM-MGCT                1 (0001)
MT62F1G32D2DS-026 WT:B         2 (0010)
K3KL8L80CM-MGCT                2 (0010)
H58G56BK7BX068                 2 (0010)

BUG=b:270103716
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Ia53c2be2ec606f42ac8bca06103b028e62ae6dbc
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
 2023-03-17 02:38:11 +00:00
Tony Huang
b3468db467 mb/google/nissa/var/yavilla: Generate SPD ID for supported memory parts 
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.

  DRAM Part Name                 ID to assign
  MT62F512M32D2DR-031 WT:B       0 (0000)
  H9JCNNNBK3MLYR-N6E             0 (0000)
  H58G56BK7BX068                 1 (0001)
  MT62F1G32D2DS-026 WT:B         1 (0001)
  K3KL8L80CM-MGCT                1 (0001)
  H58G66BK7BX067                 2 (0010)
  MT62F2G32D4DS-026 WT:B         2 (0010)
  K3KL9L90CM-MGCT                2 (0010)

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id

Change-Id: I82919919ec33d6bf9d86132490df754873b5df88
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-17 00:45:50 +00:00
Sudheer Kumar Amrabadi
0225e80061 qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLib 
This patch passes a hint flag to QcLib on Lazor boards to tell it to
limit the DDR frequency for certain memory parts (8GB Hynix) to work
around a board-specific stability issue.

BRANCH=trogdor
BUG=b:267387867
TEST=Validated on qualcomm sc7180 development board

Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
 2023-03-17 00:34:08 +00:00
Tony Huang
de2e716856 mb/google/brya: Create yavilla variant 
Create the yavilla variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVILLA

Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-17 00:33:31 +00:00
Jamie Chen
36318e116f mb/google/brya/var/omnigul: Update RAM ID table 
Add new ram_id:0010 for Micron MT62F1G32D2DS-023 WT:B.

The RAM ID table has been assigned as:
DRAM Part Name                 ID to assign
K3KL8L80CM-MGCT                0 (0000)
H58G56BK7BX068                 0 (0000)
MT62F1G32D2DS-026 WT:B         0 (0000)
MT62F512M32D2DR-031 WT:B       1 (0001)
H58G56BK8BX068                 2 (0010)
MT62F1G32D2DS-023 WT:B         2 (0010)

BUG=b:273138520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: Idc08624469590096047e5f77fb2e4ffb733f09ec
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73726
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
 2023-03-17 00:24:52 +00:00
Yunlong Jia
b2cade4f7a mb/google/skyrim/var/crystaldrift: Add 1 Micron parts to RAM ID table 
Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E．
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
    DRAM Part Name                 ID to assign
    MT62F512M32D2DR-031 WT:B       0 (0000)
    MT62F1G32D4DR-031 WT:B         1 (0001)
    MT62F1G32D2DS-026 WT:B         2 (0010)
    MT62F2G32D4DS-026 WT:B         3 (0011)
    K3LKBKB0BM-MGCP                4 (0100)

BUG=b:273177939
BRANCH=None
TEST=emerge-skyrim coreboot

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-17 00:23:34 +00:00
Jay Patel
c7728521d6 arch/x86/ioapic: Print IOAPIC ID for GSI #0 
Print IOAPIC ID for GSI #0 in logs, as part of IOAPIC initialization.

BUG=None
TEST=Confirmed "IOAPIC: ID = 0x00" printed in logs.

Signed-off-by: Jay Patel <jay2.patel@intel.com>
Change-Id: I8d8e94fe623795d059ec2abbb3319b60fd80f5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2023-03-16 15:19:10 +00:00
Joey Peng
b5fd92a14e mb/google/brya/var/taniks: Remove unused temp sensor setting 
Rwmove temp sensor 3 for taniks since we do not use it.

BUG=b:265075696
TEST=emerge-brya coreboot, flash to DUT and will not see error messages

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-16 15:00:50 +00:00
Harsha B R
68af77ea7d mb/intel/mtlrvp: Add new MTL-P board variant for MCHP1727 
This patch will add new board variant to enable MCHP1727 EC Card
for MTL-RVP

BUG=b:262800416
BRANCH=none
TEST=check if you can observe MEC EC option as part of make menuconfig.
Able to boot to ChromeOS with Microchip EC.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie0d3c37bcab5e4b90a131e17996c4b6dcbae7d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-16 14:58:19 +00:00
Zoey Wu
c9d743ca04 mb/google/brask/var/aurash: Allow USB2/3 wakeups to (un)plug events in dt 
BUG=b:271373437
BRANCH=none
TEST=Verify USB-A device could wake up Aurash.

Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: I67fc02d6c5660e0e3d1ab95bbda8ace1dc14b524
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73414
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-16 04:01:59 +00:00
Subrata Banik
7c1c0b33a5 mb/google/rex: Add Hayden Bridge (HB) to USB_DB FW_CONFIG 
This patch increases FW_CONFIG for USB_DB to 3-bits.

BUG=b:273346973
TEST=Able to build and boot google/rex with Proto 2 SKU

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib07ba1d54e7f7e2b09a99438529e503d9c9edb7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-03-15 20:06:54 +00:00
Rob Barnes
074d096ffe mb/google/dedede: Add EC_HOST_EVENT_PANIC to SCI mask 
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.

BUG=b:268377440
BRANCH=firmware-dedede-13606.B
TEST=Observe kernel ec panic handler run when ec panics

Change-Id: I24f929ae60a406d0091956dc6cab3e2876ca23e9
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 20:06:02 +00:00
Jamie Ryu
8b34c4135e mb/google/rex: Configure _DSC for camera devices 
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.

BUG=b:268607999
TEST=Build and boot rex proto1 to OS and verify privacy LED behavior.

Change-Id: Ife849f7407b02867ddb992d7eebb08b0b44aecc8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 20:05:03 +00:00
Johnny Lin
2e1624fb69 soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.c 
With newer xeon_sp processors, the concept of "north bridge" became
obsolete, instead uncore should be used. Therefore we use uncore_acpi.c
(instead of nb_acpi.c) going forward.

Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
 2023-03-15 19:59:24 +00:00
Martin Roth
0f4b2b6439 soc/amd/mendocino: MP2 firmware isn't needed in the RO image 
The MP2 firmware doesn't do anything useful when booting into recovery
mode, so don't include it in the RO image if vboot is enabled.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5afbf7e9e730e6951c416f3a3ca75f69a22099cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73660
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-15 19:37:25 +00:00
Martin Roth
0acf59d10c soc/amd: Print amdfwtool debug info if V=1 
When doing coreboot builds, we can set V=1 to see all of the make info
printed as the compile is happening. Use this flag to set the debug
flag for amdfwtool so it doesn't have to be enabled separately.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b05cbc9f9b540a174db479822af657cf35733de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73658
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-03-15 19:36:38 +00:00
Martin Roth
44217215e7 soc/amd/common: Ignore * in PSP dependency generation 
The regex getting rid of lines containing a '*' didn't match anything
in any configs, so get rid of it.  There's nothing in the amdfwtool
dataparse.c file that would match it either.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I05aaf46cfb479cebab9234a47574073335984a5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-03-15 19:36:25 +00:00
Martin Roth
d729df03ed soc/amd/common: Update PSP dependency generation 
After adding the ability to add paths into the amdfw.cfg file for the
amdfwtool, the dependency generation needs to be updated to not add
the firmware location in front of those values.

This also allows us to filter out the MP2 binaries as dependencies
based on whether or not the Kconfig value is set.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3a9b9c8246808dc60020a32a7d9d926bc5e57ccd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-03-15 19:36:12 +00:00
Karthikeyan Ramasubramanian
a18b8b44d7 mb/google/skyrim: Do not pass recovery APCB 
If recovery APCB is not passed, amdfwtool will build amdfw*.rom with
AMD_BIOS_APCB_BK entry pointing to the same offset as AMD_BIOS_APCB
entry. This will help to save 40 KiB flash space in each FW slot. On
ChromeOS, this means saving ~120 KiB flash space.

BUG=b:240696002
TEST=Build and boot to OS in Skyrim.

Change-Id: Ib3bbc1eededae20b2cd48f514722a207c46536a0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73662
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-15 17:30:19 +00:00
Lean Sheng Tan
742b65bdf6 soc/intel/tigerlake: Select X86_CLFLUSH_CAR config 
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-15 14:44:24 +00:00
Lean Sheng Tan
41546a5240 soc/intel/elkhartlake: Select X86_CLFLUSH_CAR config 
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-15 14:44:02 +00:00
Lean Sheng Tan
4c5b3f1ce7 soc/intel/coffeelake: Select X86_CLFLUSH_CAR config 
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-15 14:25:21 +00:00
Lean Sheng Tan
8615245349 soc/intel/alderlake: Select X86_CLFLUSH_CAR config 
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-15 14:25:12 +00:00
Sen Chu
0e5f51e186 soc/mediatek/mt8186: Shut down PMIC on power key long press 
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".

BUG=b:271771606
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse
BRANCH=corsola

Change-Id: I9ab35d82e57f43bac99fa8bd7bb69fcf52250311
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 10:30:17 +00:00
Sen Chu
527dd21e00 soc/mediatek/mt8188: Shut down PMIC on power key long press 
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".

BUG=b:271771606
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse

Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 10:30:05 +00:00
Dtrain Hsu
964d99ef88 mb/google/brya/var/omnigul: Correct mux_conn for USB C1 
Modify USB C1 mux_conn to 1. It should match ec settings.

BUG=b:272394875, b:272667290
BRANCH=firmware-brya-14505.B
TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi.

Change-Id: I61b77405d1790b044174cef954e5bf910141f424
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-03-15 10:11:49 +00:00
Jamie Chen
d2aacc8cd1 mb/google/brya/var/omnigul:Fixed can't detect 3.5mm headphone jack 
1. Modify irq_gpio GPP_H0 -> GPP_A23

BUG=b:272218750
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I8e178b149015ed8027b547e4c2109b3aef8a7484
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 02:24:23 +00:00
Jamie Chen
18d7f9dc53 mb/google/brya/var/omnigul:Fixed Touch screen has no action 
1. Add generic.stop_gpio = GPP_C6
2. Add c.stop_off_delay_ms = 2

BUG=b:271966059
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I33857443d8a68e7b50ac5f8f08afc017fe4f5a59
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-03-15 02:24:05 +00:00
Frank Wu
23c77ef0c3 mb/google/skyrim/var/frostflow: Update the STT settings 
According to file thermal_table_0310, adjust the STT settings.

BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.

Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
 2023-03-14 01:42:37 +00:00
Amanda Huang
48286abfc1 mb/google/dedede/var/dibbi: Configure I2C times for audio 
Configure the I2C bus high and low time for audio.

BUG=b:271804915
BRANCH=dedede
TEST=Build and confirm I2C clock for audio is between 380 kHz and 400
kHz

Change-Id: I2987a39abc5527844424edfa1cf70d5c5cea5357
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2023-03-14 01:23:06 +00:00
van_chen
e5fa3b1680 mb/google/brya: Create uldren variant 
Create the uldren variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:271513530
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ULDREN

Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-03-14 01:22:57 +00:00