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1ac19e28eed4f6c53a4f295eb55500c65fc80f8d
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3 Commits

Author SHA1 Message Date
Keith Hui
1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.

Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.

Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.

Also change Deschutes CPU init sequence to match Katmai.

Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2011-08-04 08:10:12 +02:00
Stefan Reinauer
c104cb0d9d update intel microcode files. 
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-10-18 00:21:39 +00:00
Keith Hui
b14fb6abd6 Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. 
abuild-tested. I have no Deschutes CPUs to boot test this with.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2010-10-16 08:45:31 +00:00