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Author SHA1 Message Date
Rizwan Qureshi
8ae5418853 mb/google/hatch: Enable Host Bridge/CSME/PMC/P2SB/SMBus 
* Enable host bridge.
* Enable CSME.
* Enable Power Management Controller.
* Enable Primary to Side Band Bridge Controller.
* Enable SmBus Controller.

BUG=b:120914069
BRANCH=None
TEST=code compiles with the changes

Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-29 04:33:01 +00:00
Krystian Hebel
fba0320842 mb/pcengines/apu2/romstage.c: disable SVI2 wait completion 
On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.

Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2018-12-28 22:39:40 +00:00
Elyes HAOUAS
69b6c56909 util/xcompile/xcompile: Use tab for indent 
Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2018-12-28 22:33:30 +00:00
Elyes HAOUAS
14df1b0eeb superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white spaces 
Change-Id: I8a5d937bfc1e0ff61736c19a24b03c1a8defc427
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-12-28 22:32:48 +00:00
Matthew Garrett
2bf28e52ee util/inteltool: Add support for Sunrise Point LP 
Used documents:
334658 (Sunrise Point-LP I/O datasheet vol. 1)
334659 (Sunrise Point-LP I/O datasheet vol. 2)
332690 (Sunrise Point I/O datasheet vol. 1)

Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/28623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2018-12-28 22:31:54 +00:00
Elyes HAOUAS
6ece0adf8c intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spaces 
Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-12-28 13:13:46 +00:00
Elyes HAOUAS
2ea751a588 arch/x86/c_start.S: Use tabs instead of white spaces 
Change-Id: I415993bf11f6a019ff8ef4c0cba3b5bb511271fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30453
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 13:12:36 +00:00
Elyes HAOUAS
dea45c1060 drivers/amd/agesa/cache_as_ram.S: Fix coding style 
Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2018-12-28 13:10:39 +00:00
Elyes HAOUAS
2cc351da5f src/cpu/intel/model_f4x: Update cpu_table 
CPUID 0xf47 tested on on 945G-M4 board.
Needs more MSR's consistency tests.

To do: test if speedstep.c and speedstep/acpi.c
are ok for model_f4x.

Change-Id: I285ad33804592e3df510d61dd24f14f944e05142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/17409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-28 12:26:08 +00:00
Matt DeVillier
680ed1f632 ec/chromeec: fix LPC read/write for MEC devices 
Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface]
changed the return mechanism for the checksum on reads/writes
for MEC devices, but incorrectly handled the passed-in csum
parameter by not dereferencing. This led to the returned csum
value always being zero, which causes all EC commands with non-
NULL data_in to fail with a checksum error.

Fix this by storing the returned checksum in a temp variable,
and only assigning to csum when the pointer isn't NULL;

Test: build/boot google/chell, verify EC hello command succeeds,
keyboard backlight turned on at boot.

Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-28 12:24:52 +00:00
Ren Kuo
337afb0567 mb/google/poppy/variant/nami: add the vbt setting for bard sku 
Modify the vbios's eDP signal setting from level0(0dB)
to level1 (3.5dB) for bard
Add VBT blobs and include it in cbfs

BUG=b:119448457
TEST=Test & measure eDP signal

Change-Id: I0b854a6adad43844282aed61d26e798727b5cb62
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30375
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 12:24:20 +00:00
Arthur Heymans
322f76dfbf intel/gma/Makefile.inc: Add a helper function to add VBT binaries 
This adds a convenient helper function to add vbt binaries to cbfs.

Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30430
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 12:23:57 +00:00
Tristan Corrick
d3f01b21fa sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports 
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root
ports, all others have 8 [1]. The existing PCIe code assumed that all
non-LP chipsets had 8 root ports, which meant that port 6 would not be
considered the last root port on H81, so `root_port_commit_config()`
would not run. Ultimately, while PCIe still worked on H81, all the root
ports would remain enabled, even if disabled in the devicetree.

Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they
are unused, and the MAX constant is incorrect.

Interestingly, this fixes an issue where GRUB is unable to halt the
system.

Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree
do indeed end up disabled.

[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
    (PCH) Datasheet, revision 003, document number 328904.

Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30077
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 12:22:35 +00:00
Bora Guvendik
c54d52d67d mb/google/octopus: Override emmc DLL values for Phaser 
New emmc DLL values for Phaser.

BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test

Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30144
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 12:21:30 +00:00
Kane Chenffd
b3591f3982 mainboard/google/poppy/variants/rammus: Fixed touchscreen function failed 
According to issue tracker b:119238959 #4 & #6.
Hardware modify design to make GPP_E3 to be a switch of touchscreen
I2C CLK and SDA.
Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during
power on initialization to avoid data transfer during this time.
After touchscreen IC initial complete, control GPP_E3 to high to
make touchscreen I2C CLK and SDA work normally.
Depending on touchscreen IC specification, device take 105ms for
power on initialization.
Change delay time from 120ms to 105ms.


BUG=b:119238959
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, run S5 stress test and verify the result

Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86452c1445243c499aeaf931dba286db169c5628
Reviewed-on: https://review.coreboot.org/c/30180
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 12:21:22 +00:00
Kyösti Mälkki
c21df03ab6 arch/x86: Drop spurious arch/stages.h includes 
Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-28 06:47:31 +00:00
Rizwan Qureshi
3736127c97 mb/google/hatch: Enable SPI controller for Hatch 
Enable SPI controller(D31:F5).

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2018-12-28 06:45:21 +00:00
Kyösti Mälkki
3c0c3619bc arch/x86: SSE2 implies SSE support 
Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2018-12-28 06:41:29 +00:00
Maulik V Vaghela
8f537442d5 mb/google/hatch: Enable console UART 
This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.

Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2018-12-28 06:39:14 +00:00
Aamir Bohra
3b1a42f95d mb/google/hatch: Enable LPC/eSPI controller 
Enable LPC/eSPI controller(D31:F0). EC would be using
eSPI interface, since the strap GPP_C5 is pulled up.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2018-12-28 06:38:10 +00:00
Elyes HAOUAS
afc63844e2 src/northbridge: Get rid of device_t 
Use of device_t is deprecated.

Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2018-12-28 05:40:56 +00:00
Kyösti Mälkki
acaa581a47 soc/intel: Drop romstage_after_car() 
Platforms moved to POSTCAR_STAGE so these are no longer used.

Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-28 05:27:20 +00:00
Aamir Bohra
049ad67f76 mb/google/hatch: Add SMI handlers 
Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-27 22:08:57 +00:00
Maulik V Vaghela
04a7ce728d mb/google/hatch: Add HPD GPIO support for displays 
Adding hot plug detect GPIO support for external Type-C display in event for
cable connect/disconnect.

Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30365
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:44:11 +00:00
V Sowmya
656015c258 mb/google/hatch: Modify hatch SPI flash layout 
This patch modifies the hatch flash layout to support
IFWI 1.6 with the following regions,
Flash Region 0: Descriptor
		[0x0 - 0xFFF]
Flash Region 1: IFWI (consist of ME and PMC FW)
		[0x1000 - 0x3FFFFF]
Flash Region 2: BIOS
		[0x1400000 - 0x1FFFFFF]

Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30413
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:43:34 +00:00
Aamir Bohra
6aaae1c893 mb/google/hatch: Enable EC LPC interface and configure IO decode range 
Enable EC LPC interface and configure below LPC IO decode ranges:

1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-25 03:42:59 +00:00
Aamir Bohra
0dfda74408 mb/google/hatch: Add SoC and EC asl files in DSDT 
This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-25 03:42:23 +00:00
Aamir Bohra
3a167f56f4 mb/google/hatch: Add EC trigger events and acpi configs 
This implemetation adds EC SCI, SMI, S5/S3 wake trigger events.
Also adds the EC specific ACPI configs to enable support for ALS,
EC PD device and PS2 keyboard device.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-25 03:41:46 +00:00
Arthur Heymans
7592c3a317 soc/intel/*: Select SUPPORT_CPU_UCODE_IN_CBFS only once 
This was selected twice.

Change-Id: I7e20b7d3f05ecae98db1addf5aea7bf1159f4682
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2018-12-24 18:19:53 +00:00
Kyösti Mälkki
43b8155352 Remove intel/skylake/bootblock/timestamp.inc 
Platform has been moved to C_ENVIRONMENT_BOOTBLOCK and this
file was for romcc bootblock.

Change-Id: I2c249b18edd41c9a7798400d24b1c9228422d59b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-24 08:19:21 +00:00
Kyösti Mälkki
87efe24cce soc/intel/quark: Drop BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP 
This was empty stub call doing nothing, to avoid targeting
non-existing MMX registers.

Change-Id: I78b83e6724159ea1eb0f8a0cf9d5b7ddfc9877b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-24 08:19:08 +00:00
Arthur Heymans
3534c1e42d mb/asus/p5qpl-am: Add mainboard 
This mainboard has the BSEL straps hooked up to the SuperIO
similar to the ASUS P5GC-MX and might therefore require a restart.

Tested:
- FSB 800, 1067 and 1333MHz CPUs
- USB
- Ethernet
- Serial
- 2 DIMM slots
- SATA
- Libgfxinit (VGA)

TESTED with SeaBIOS (sercon disabled) and Linux 4.19.

Change-Id: Id845289081751ff8900e366592745f16d96f07c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2018-12-24 08:18:16 +00:00
Arthur Heymans
ba5e70e967 driver/spi/eon.c: Add EN25F80 
TESTED on ASUS P5QPL-AM (writes MRC_CACHE)

Change-Id: I5aebe4703a033a0f0226f405d8933b12f3af136f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-24 08:17:24 +00:00
Elyes HAOUAS
2397bafec5 arch/x86/wakeup.S: Use tabs instead of white spaces 
Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-24 08:17:00 +00:00
Elyes HAOUAS
f661b4df3b arch/arm/memmove.S: Use tabs instead of white spaces 
Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-24 08:16:54 +00:00
Elyes HAOUAS
9981df3dde x86/smm/smmhandler.S: Use tabs instead of white spaces 
Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-24 08:16:48 +00:00
Elyes HAOUAS
6d772bc6c3 car/non-evict/exit_car.S: Use tabs instead of white spaces 
Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-24 08:16:44 +00:00
Tristan Corrick
cbc561f64a Documentation/nb/intel: Add Haswell documentation 
At the moment, this just gives some details on the MRC.

Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2018-12-24 08:16:06 +00:00
Tristan Corrick
a26b02466e drivers/aspeed/ast: Select MAINBOARD_HAS_NATIVE_VGA_INIT 
Any board that uses the AST driver will have support for native graphics
init. So, select the option in the driver instead of every board.

Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2018-12-24 08:15:49 +00:00
Paul Menzel
409dc3b2c0 sb/amd/cimx/sb800/ramtop: Fix coding style issues 
Let GNU indent 2.2.11 fix the coding style issue with `indent -linux …`.

Change-Id: Ia2d48906bbeb5ec2f3bea6a93fd2a06aa76b29d9
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/19458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 2018-12-24 08:15:18 +00:00
Patrick Rudolph
3f4ed7a40b soc/intel/fsp_broadwell_de/acpi: Fix wrong table checksum 
Fix the following warning shown in dmesg:
"ACPI BIOS Warning (bug): Incorrect checksum in table [FACP]"

The table checksum was wrong as it was calculated twice and with the second
time the checksum field wasn't set to zero.

Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2018-12-24 08:14:54 +00:00
Sumeet Pawnikar
56db59c91a Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings" 
This reverts commit 969ed357f8

Reason for revert:
According to partner issue b:112448519 comment#80, it impacts
skin temperature specifications.

Change-Id: I7603c3816f34adebc1f67eff6fad214557544022
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
 2018-12-24 08:14:10 +00:00
Frans Hendriks
e1700fc832 util/cbfstool/cbfstool.c: Fix typo 
Fix typo of 'top-aligned'

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I6dc2f150d8ec245070257384b406a570498400b2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30337
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-24 08:13:48 +00:00
Maulik V Vaghela
2fe81b2810 mb/google/hatch: Enable IGD (Integrated GFX Device) 
This patch ensures following 2 features
1. Enable IGD controller in devicetree.cb
2. Pass required FSP UPD to perform internal graphics initialization

Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-23 05:12:52 +00:00
Aamir Bohra
4b85d46170 mb/google/hatch: Add memory init setup for hatch 
This implementation adds below support:

1. Add support to read memory strap.
2. Add support to configure below memory parameters
   -> rcomp resistor configuration
   -> dqs mapping
   -> ect and ca vref config
3. Include SPD configuration

BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot

Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-23 05:12:14 +00:00
Shelley Chen
09e7b99837 mb/google/hatch: Enable Elan Trackpad 
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc" emerge-hatch coreboot

Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2018-12-22 12:14:39 +00:00
Shelley Chen
6bb563f29c mb/google/hatch: Fixes to initial hatch mainboard checkin 
Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.

Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB

BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v

Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-22 12:14:20 +00:00
Kyösti Mälkki
74e0390e74 cbmem: Always use EARLY_CBMEM_INIT 
Wipe out all remains of EARLY/LATE_CBMEM_INIT.

Change-Id: Ice75ec0434bef60fa9493037f48833e38044d6e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2018-12-22 11:49:17 +00:00
Kyösti Mälkki
513a1a81f7 arch/x86 cbmem: Drop tests for LATE_CBMEM_INIT 
Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.

This also removes all references to LATE_CBMEM_INIT
in comments.

Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-22 11:48:37 +00:00
Arthur Heymans
8616442150 soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGE 
Tested on wedge100s.

Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29911
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-12-22 11:47:25 +00:00