The MT8183 display serial interface (DSI) is based on MIPI
Alliance Specification, supporting high-speed serial data
transfer between host processor and peripheral devices such
as display modules.
DSI supports both video mode and command mode data transfer
defined in MIPI spec, and it also provides bidirectional
transmission with low-power mode to receive messages from
the peripheral.
Reference: MT8183 Application Processor Functional Spec,
6.7 Display Serial Interface (DSI)
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For systems with real MIPI panels (8173/oak was using PS8640 eDP
bridge), we have to send DCS commands to initialize panel.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The video timing should be based on PHY timing. Some values can be
ignored on 8173 because of fixed values in PHY but should be calculated
for newer platforms like 8183.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The PHY timing should be calculated by data rate (Mbps). However for
8173 some values were hard-coded so we want to introduce a new
mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing
that allows per-SOC customization to apply PHY timings.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add code to read SPD data, parse it and save into SMBIOS table. This is
implemented for socketed DDR4 chips only. For soldered-down memory this
is not implemented and probably won't be ever needed.
TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to
work. The stack has also been tested on an out-of-tree board.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table
17. XMP, schemas, extended field parising is totally not yet implemented.
Also, put CRC function used in DDR2, DDR3 and DDR4 ina common file.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
IMC is found on certain Xeon processors. On such platforms SPDs are not
connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose
of this driver is to expose access to the i2c/smbus controller associated
with IMC.
Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2,
reference 332051-001
This driver is largely based on i2c-imc.c Linux driver.
https://lwn.net/Articles/685475/
TEST=single/double reads and single writes on Xeon-D1500.
Hardware: Open Compute Project Monolake platform.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34678
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use internal UART it needs to 'enabled'. This is normally done
by FSP. However sometimes internal UART is needed before FSP is invoked.
TEST=check if printk() show up in early romstage. Tested on OCP Monolake.
Tested on out-of-tree mainboard to see if UART on LPC still works.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I88a7b1a38abf9a09137f6dd75a5a9dee104daaca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34683
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for allowing devices to provide a
"compatible" property string that can be used when _HID is set to
PRP00001. This is used to allow Linux kernel drivers to match the
device to appropriate driver based on the OF-style compatible
string.
Reference:
https://www.kernel.org/doc/Documentation/acpi/enumeration.txt
BUG=b:129162037
TEST=Verified that atmel touchscreen gets enumerated correctly on
kohaku using PRP0001 and compatible string.
Change-Id: I8a306854c67ab2f056ea8774df46599ef0c55761
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This change updates the Atmel touchscreen ACPI node to use PRP0001 as
_HID to allow OF-style compatible string matching for enumeration.
Reason for this change: Atmel touchscreen driver in Linux kernel looks
for "compatible" property to decide if it is okay to attach to the
device. This check seems to be a protection against old firmware in
the field that do not have the right properties.
BUG=b:129162037
TEST=Verified that touchscreen works on Kohaku.
Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The only platform-specific difference in mtk_dsi_phy_clk_setting is how
to configure MIPI TX because those registers (and logic) are quite
different across different SOCs.
The calculation of data rate is actually the same so we should isolate
it and move to common, and rename mtk_dsi_phy_clk_setting to a better
name as mtk_dsi_configure_mipi_tx.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The 'bpp' was referred to both 'bits per pixel' and 'bytes per pixel' in
MTK DSI driver and should be corrected. By this change we now always
consider 'bpp' as 'bits per pixel', and rename the variables for other
cases.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34770
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DSI initialization is almost the same for 8173 and 8183, so we want
to move most of common functions into common/dsi.c.
The major board-specific functions left are:
- reset (controller register has different format)
- pin_drv_ctrl (8183 does not need this)
BUG=b:80501386,b:117254947
TEST=make -j # board=oak (mt8173)
Change-Id: I8d4369a3c84db551287a9c9d1b22f552c5f7518d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Build error on missing vb2ex_printf() in bootblock stage
Add the file vboot_logic.c which contains the missing vb2ex_printf().
BUG=N/A
TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701
Change-Id: I3f649f3faf1e812d592e4981bc75698e2cad1cc8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The Kohaku V24 schematic adds two additional temperature sensors
to the EC. Add these to the DPTF tables.
Cq-Depend: chromium:1742914
BRANCH=none
BUG=b:138578073
TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel.
1. Build EC
``cd ~/trunk/src/platform/ec``
``make -j BOARD=kohaku``
2. Program EC
``./util/flash_ec --board=kohaku``
3. Reboot device
4. Rebuild BIOS
``cd ~/trunk/src/third_party/coreboot``
``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge
vboot_reference libpayload coreboot-private-files intel-cmlfsp
coreboot-private-files-hatch coreboot chromeos-bootimage``
5. Use flashrom to program the BIOS
6. Reboot device
7. Log into the root console (ctrl-alt-F2 or servo)
8. Example thermal sensor information
``grep . /sys/class/thermal/t*/type``
Look for "TSR0" through "TSR3" in the output.
Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Oops, I missed this in the last CL.
The pin needs to be configured as owned by GPIO, so that the kernel
driver can bind it with an IRQ.
BUG=b:139165490
TEST=Ensure kernel nastygram about inability to claim the IRQ is gone
Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In general, third party code (such as vboot) doesn't know what the
underlying types are for the integers in <stdint.h>, so these macros are
useful for portably printing them. Of these definitions, coreboot so far
has only used PRIu64 (in one place), which isn't needed anymore since we
know what the underlying type of a u64 is.
Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change the stoneyridge definitions into picasso. The named 0 and 1
buses are controlled by the PSP and not directly accessible by host
firmware. I2C4 operates only in slave mode so is not added to to
the bus clear-after-reset sequence.
The I2C controller is fundamentally the same as on Stoney Ridge so
the ability to clear a potentially jammed bus is still required.
Program Picasso's new pad control registers in the MISC AcpiMmio
space according to the recommended settings.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
