This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload.
This left MIE set to an undefined value.
Now all modes are handled the same way:
- Trap vector base address point to the payload
- Disable Interrupt
- Return to payload using mret
TEST=Run an M-mode payload
Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs
to be configured.
Add mainboard_configure_edp_bridge() to program the controller.
CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block
write:
<Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB
first.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add chips ops for IPMI KCS.
* Get IPMI version over KCS.
* Generates ACPI SPMI table for IPMI KCS.
* Generates SMBIOS type 38 for IPMI KCS.
* Generates ACPI SPMI device for IPMI KCS on LPC device.
* Add documentation
To use this driver on BMC that support KCS on I/O:
1. Add an entry to the devicetree.cb:
chip drivers/ipmi
device pnp ca2.0 on end # IPMI KCS
end
2. Select IPMI_KCS in Kconfig.
3. (Optional) enable LPC I/O decode for the given address.
Tested on Wedge100s.
Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Garg proto build has 3 SKUs:
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Cq-Depend: chrome-internal:1380847
Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The compat string matching code was mostly copied from depthcharge. One
of the few differences is that we now store the list of compat strings
we're willing to match in a list rather than an array. Since our lists
insert at the front, that means the strings are now ordered lowest to
highest (not highest to lowest like in depthcharge).
We did rewrite the compat_rank matching code to accomodate for that...
however, what we didn't do is remove the break-statement in the loop
that matches all compat strings. When we search the lowest priority
first, we can't abort the search as soon as we found a match -- we have
to keep looking because we might find a higher priority match later.
This patch fixes the issue so that my Kevin can actually match for
google,kevin-rev5 (and doesn't just jump at the first best google,kevin
match).
Change-Id: Ibe3d84bbce6de3cd49c746a667ae1ccfdc843105
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32874
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to boot FIT image configurations consisting of
a base device tree and one or more overlays. Since extracting the right
compatible string from overlay FDTs is problematic, we'll only support
this for FIT images that have the compatible string pulled out into the
config node.
This patch was adapted from depthcharge's http://crosreview.com/1555293
Change-Id: I0943f9a1869c9e416887c7ff16e33f7d91b74989
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32873
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for compressing individual device trees in the
FIT image. In order to make this efficient, we'll have to pull the
compatible property out of the FDT and store it directly in the config
node of the FIT image, so that we don't have to scan (and therefore
decompress) every single FDT on boot. Device tree compression is only
supported for FIT images that have this external compatible property.
For older images with no compression, we still support fallback to
scanning the FDT for the property.
This patch was adapted from depthcharge's http://crosreview.com/1553458
Change-Id: Ifcb6997782c480c8ef6692df17b66ad96264e623
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32872
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel handoff on all architectures supporting FIT images already
includes flushing and disabling the cache. No need to waste any more
time flushing individual components (especially since in the case of
compressed DT overlays they will still get accessed again afterwards).
Change-Id: I7b483e920c5a71663b024b5b50804ffc84939830
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32871
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes some minor refactoring to the way the FIT parser
handles config nodes. A lot of this code was written in the dawn age of
depthcharge when its device tree library wasn't as well-stocked yet, so
some of it can be rewritten nicer with more high-level primitives.
There's no point in storing both the string name and the actual FDT node
of a FIT image node separately, since the latter also contains the
former, so remove that. Also eliminate code for the case of not having
an FDT (which makes no sense), and move some more FDT validity/compat
checking into fit_update_compat() (mostly in anticipation of later
changes).
This patch was adapted from depthcharge's http://crosreview.com/1553456
with a couple of modifications specific to coreboot's custom FIT loading
code.
Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code is based on microcode update procedure from fam10-15h with necessary
microcode blob structure updates for fam16h.
Currently updating microcode in romstage seem to be impossible. AGESA is
overriding the microcode patch regardles of the current microcode revision
patched on CPU. Use ramstage CPU init procedures to update microcode easily.
Tested with microcode blob 07030106 released 2018-02-09 from
platomav/CPUMicrocodes GitHub repository on apu2 platform.
TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see
patch_level=0x07030106 on all cores
Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DIMM manufacturing ID was not being initialized and so the DIMMs
were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects
SPD module type values from DDR2 so the DDR3/4 values are adjusted
before sending to SMBIOS.
BUG=b:134897498
BRANCH=sarien
TEST=dump and compare with dmidecode
BEFORE:
Type: DDR4
Manufacturer: Unknown (0)
Form Factor: Unknown
AFTER:
Type: DDR4
Manufacturer: Hynix/Hyundai
Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This function attempts to set bits in the 20s of state and state_save,
which won't work since those variables are only 16 bits wide. Extend
them to 32 bits to capture all the bit operations.
Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
