d789b658f7
nb/intel/i945/raminit: Use boolean type for helper variables
...
Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-15 13:01:09 +00:00
842dd3328d
nb/intel/i945/raminit: Remove space for correct alignment
...
Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-03-15 13:00:54 +00:00
f897623aac
mb/asus/p8z77-m_pro: Use uppercase for *PRO*
...
Consistently use the official uppercase spelling.
Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 13:00:07 +00:00
fac491dab7
Docs: Fix link for ASUS P8Z77-M PRO
...
Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-15 12:59:52 +00:00
599bc6070d
lib/spd_bin: Add spaces around operator
...
Change-Id: Ic0571d06e94708dd5e151621ab7790f3c9f775c2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-15 12:57:20 +00:00
dd57ac2f35
soc/intel/icelake: Re-flow comment for 96 characters
...
Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-15 12:57:02 +00:00
9f11185920
soc/intel/icelake: Correct past participle in comment
...
Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-15 12:56:48 +00:00
655dba4055
soc/intel/tigerlake: Match RP number with TGL EDS
...
Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.
BUG=b:151208838
TEST=build RVP successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
2020-03-15 12:56:21 +00:00
4d5fd77cf8
lib/spd_bin: Cleanup spd_get_banks
...
Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-03-15 12:56:09 +00:00
cb1e386eab
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs
...
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-03-15 12:56:01 +00:00
a6bff2d8ab
soc/intel/tigerlake: Enable CNVi through dev_enabled
...
Check for dev enabled status for CNVi and update the
UPD accordingly.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2020-03-15 12:55:19 +00:00
4b9fa2d6ea
soc/intel/tigerlake: Update Cpu Ratio settings
...
Add config to override CpuRatio or setting CpuRatio to
allowed maximum processor non-turbo ratio.
BUG=151175469
BRANCH=none
TEST=Build and boot tglrvp and observe there is no extra reset
in meminit.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 12:54:40 +00:00
1db5bc7dac
nb/intel/haswell: Tidy up code and comments
...
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 12:54:00 +00:00
3663d55a23
mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
...
Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 12:53:33 +00:00
1f4f0b47f5
mb/google/hatch: Create palkia variant
...
Add Palkia as a variant of Hatch.
BUG=b:150254194
BRANCH=none
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com >
Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 12:53:13 +00:00
aeaeeb7687
mb/google/volteer: Use generic SPD files
...
Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-15 12:52:54 +00:00
ee47fe42f5
soc/intel/tigerlake: Configure Vmx support using Kconfig
...
Change VmxEnable UPD value based on Kconfig ENABLE_VMX
BUG=None
TEST=Built image and booted to kernel.
Change-Id: I725474643193223865a135813cf882fd7636d24a
Signed-off-by: John Zhao <john.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
2020-03-15 12:52:26 +00:00
6e5693386b
coreboot: add Volteer template files
...
Add template files for making a new barebones-copy of Volteer.
BUG=b:147483699
BRANCH=None
TEST=N/A
Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2020-03-14 23:41:14 +00:00
f354c8c625
mb/google/dedede: Configure WLAN
...
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-03-14 23:31:05 +00:00
136e0cbbc1
mb/google/dedede: Add BT Disable GPIO configuration
...
Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-14 23:29:30 +00:00
f9c6a8821f
mb/google/drallion: Enable GEO SAR
...
Enable GEO SAR function.
BUG=b:150347463
BRANCH=drallion
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org >
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-14 23:28:06 +00:00
c04757b108
mb/intel/tglrvp: Update GPIO setting
...
Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.
BUG=b:151305120
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-14 23:27:00 +00:00
dabc0adb3a
ec/google/chromeec/acpi: Move ECPD under CREC
...
Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP
device drivers can access the parent EC device to communicate with the
EC. Also, update the Notify() call to reflect the new location of the
ECPD device.
Signed-off-by: Prashant Malani <pmalani@chromium.org >
Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2020-03-14 02:42:35 +00:00
22d5b07160
mb/google/volteer: Enable Audio DSP UPD
...
Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-13 18:31:17 +00:00
6daa8c3ba5
mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff
...
Early ec sync needs to be disabled for EFS2 to function.
BUG=b:151115320
BRANCH=none
TEST=none
Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-03-13 02:50:21 +00:00
49111cd2ba
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
...
Tigerlake platform supports Virtualization Technology for Directed I/O.
Enable VT-d feature and generate DMAR ACPI table.
BUG=None
TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI
remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and
"iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e
Signed-off-by: John Zhao <john.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
2020-03-12 21:36:57 +00:00
a7ec42619c
soc/intel/*/smihandler: Only compile in TCO SMI handler if needed
...
commit 7f9ceefpgeorgi@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Michael Niewöhner
2020-03-12 21:36:20 +00:00
4f8b00602c
mb/google/dedede: Enable trackpad support
...
1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.
TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.
Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2020-03-12 07:41:25 +00:00
d1f3022ebf
mb/google/hatch: Create nightfury variant
...
Create new variant and build for nightfury.
BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Shelley Chen <shchen@google.com >
2020-03-12 07:41:10 +00:00
396bb46e7d
mb/google/volteer: configure L1Substate for PCIe
...
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2020-03-12 07:40:45 +00:00
84b4882b99
soc/intel/tigerlake: Configure L1Substates for PCH Root ports
...
Set value for PcieRpL1Substates according to devicetree.
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-12 07:40:11 +00:00
9a2922871d
vboot: remove extraneous vboot_recovery_mode_memory_retrain
...
Just call get_recovery_mode_retrain_switch() directly.
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a
Signed-off-by: Joel Kitching <kitching@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-12 07:39:47 +00:00
18129f919a
soc/intel/tigerlake: Enable HDA through dev_enabled
...
Check for dev enabled status for HDA controller and
update the UPD accordingly.
BUG=151174264
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-12 07:38:50 +00:00
6f785b0f62
mb/google/dedede: Add ACPI configuration for USB ports
...
Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Justin TerAvest <teravest@chromium.org >
2020-03-11 19:58:06 +00:00
f787e87145
mb/intel/tglrvp: Enable Hybrid storage mode
...
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
2020-03-11 19:57:44 +00:00
ccde6be13a
soc/intel/common/block/smm: add case intrusion to SMI handler
...
This adds case intrusion detection to the SMI handler. At this point one
can add the code to be executed when the INTRUDER signal gets asserted
(iow: when the case is opened).
Examples:
- issue a warning
- trigger an NMI
- call poweroff()
- ...
Tested on X11SSM-F.
Change-Id: Ifad675bb09215ada760efebdcd915958febf5778
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2020-03-11 15:36:31 +00:00
5f26d8cb4a
mb/google/dedede: Add SPD hex file for Samsung memory part
...
BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-11 15:12:46 +00:00
cb858d6d62
superio/nuvoton/nct5539d: Update documentation and remove DSDT
...
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-11 15:03:39 +00:00
6dc488a678
drivers/intel/gma/acpi: Prevent DivideByZero error
...
In case backlight control isn't enabled BCLM is zero.
Return early instead of running into a DivideByZero error.
This happens on devices that don't have backlight control, like
desktops and servers. The proper fix is to not include those
ACPI methods, but that requires a much bigger refactoring.
Change-Id: Ie9bdb00949d6d44fd99321db556d6008d2d12a7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-03-11 14:50:35 +00:00
a02f00e5d6
soc/intel/tigerlake: Save DIMM info by available nodes
...
TEST=Verified that dmidecode produces output identical to private repo
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com >
Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-11 14:43:25 +00:00
fe2a4c1001
mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C
...
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com >
2020-03-11 14:42:13 +00:00
6bc471461b
mb/google/hatch: Add LP_4G_2133 SPD
...
Add LPDDR3 4GB 2133MHz SPD file.
BUG=b:149226871
TEST=Build and check cbfs has the spd.bin
Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com >
Reviewed-by: Philip Chen <philipchen@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-11 14:41:05 +00:00
c34bb3807c
mb/google/volteer: Enable pcie rp11 for optane
...
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com >
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-03-11 14:39:06 +00:00
35d7843799
soc/intel/tigerlake: Correct FSP log interface
...
select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set
"PcdDebugInterfaceFlags" UPD accordingly.
BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP UART log
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
2020-03-11 14:38:17 +00:00
840bef061f
soc/intel/tigerlake: Fix stale device pointer usage
...
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
2020-03-11 14:37:28 +00:00
a53dbd4780
mb/google/volteer: Disable WWAN PCIe
...
Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.
BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device
Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-03-11 14:37:01 +00:00
0965044c99
commonlib/cbfs.c: Remove unused macro
...
Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2020-03-11 14:36:45 +00:00
04e0712f46
Treewide: Add some gcc's warning options
...
Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2020-03-11 14:36:24 +00:00
66815114cf
mb/intel/tglrvp: sync up variant folders with latest up3
...
During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4
BUG=none
BRANCH=none
TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com >
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com >
2020-03-11 14:33:16 +00:00
2bd2be545f
soc/intel/common/block: tco: enable intruder SMI if selected
...
Set TCO to issue an SMI when the case instrusion switch gets pressed.
The SMI is controlled along with the general TCO SMI Kconfig.
Tested on X11SSM-F.
Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-03-11 14:28:53 +00:00
