Commit Graph

784 Commits

Author SHA1 Message Date
Arthur Heymans
4513020064 cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09 09:56:06 +00:00
Elyes HAOUAS
909870aba6 cpu/intel/common: Fix generated exception if not supported VMX
Reading rdmsr(IA32_FEATURE_CONTROL) in function set_feature_ctrl_lock()
will generate an exception if the CPU do not support this MSR.
Tested on pentium4 (CPUID F65).

Change-Id: I72e138e3bcffe1dcd4e20739a8d07c9abfab4f80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-01-09 09:49:50 +00:00
Arthur Heymans
8c70dd66da cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF
The value of %ebx was clobbered later on by a cpuid call.

A bitwise and needs to be used to check processor flags.

Change-Id: I29f1fddfe3cc2cbfc7c843b6aff7425f32e12317
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09 04:07:29 +00:00
Arthur Heymans
0eb9c57049 arch/x86: Link walkcbfs.S instead of including it
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.

This is useful for cbfs access in pre-CAR environments.

Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08 15:41:51 +00:00
Arthur Heymans
ad80e7f118 cpu/intel/car/bootblock.c: Report BIST failures
The result is saved in a static variable and is reported when the
console is initialised.

Change-Id: I5f0f9edce68634adfe4a77a0d2c0bf3d7cd4e78e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08 15:37:18 +00:00
Arthur Heymans
d3d82e09fc cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCK
Add common C entry points that hook to platform-specific
bootblock code.

Change-Id: I8eac974864f255811e8708997a8014a45a5c09ee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08 15:35:08 +00:00
Kyösti Mälkki
c641f7ed9f cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.

Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08 15:33:47 +00:00
Kyösti Mälkki
c70eed1e62 device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06 01:17:54 +00:00
Matt DeVillier
54efaae701 cpu/intel/common: improve debug output
currently, if the IA32_FEATURE_CONTROL lock bit is already
set, VMX status isn't reported. Adjust debug output to
provide more useful infomation on both VMX and lock bit statuses.

Test: build/boot google/chell, observe useful output in cbmem log
regardless of lock bit status.

Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-05 20:39:23 +00:00
Tristan Corrick
334be3289d nb/intel/haswell: Add support for PEG
This means that any PCIe device placed in a PEG slot should now work.

During S3 resume, link training sometimes does not complete before
device enumeration. However, no tangible issues have been observed.
Fixing it would introduce a rather large delay in S3 resume.

There are a few minor shortcomings:

- Using PEG for display output is not yet supported.
- Only PEG2 is supported. An extra (unknown) training sequence is said to
  be needed for PEG3.
- The ACPI _PRT method is not yet generated, so legacy interrupt routing
  doesn't work for devices with multiple functions.

Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works
under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the
PEG slot, and it appears functional.

[1]: https://wiki.archlinux.org/index.php/PRIME

Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03 18:11:54 +00:00
Arthur Heymans
2e658f8edf src/cpu/microcode: Add code to update microcode in assembly
Add code to update microcode from cbfsfiles using assembly.

Change-Id: I8bd192f3f345651db0010239f99293ae63b00652
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-31 21:36:02 +00:00
Kyösti Mälkki
d7892bc391 arch/x86: Add CAR stack location symbols
Add symbols for the non C_ENVIRONMENT_BOOTBLOCK builds
and use them for stack guards.

Change-Id: Ib622eacb161d9a110d35a7d6979d1b601503b6f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30 12:36:30 +00:00
Kyösti Mälkki
a75ab2c46d cpu/intel/car: Drop remains of setup_stack_and_mtrrs()
Platforms have moved to POSTCAR_STAGE=y.

Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30 11:42:07 +00:00
Elyes HAOUAS
2cc351da5f src/cpu/intel/model_f4x: Update cpu_table
CPUID 0xf47 tested on on 945G-M4 board.
Needs more MSR's consistency tests.

To do: test if speedstep.c and speedstep/acpi.c
are ok for model_f4x.

Change-Id: I285ad33804592e3df510d61dd24f14f944e05142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/17409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28 12:26:08 +00:00
Kyösti Mälkki
3c0c3619bc arch/x86: SSE2 implies SSE support
Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-28 06:41:29 +00:00
Kyösti Mälkki
acaa581a47 soc/intel: Drop romstage_after_car()
Platforms moved to POSTCAR_STAGE so these are no longer used.

Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28 05:27:20 +00:00
Elyes HAOUAS
6d772bc6c3 car/non-evict/exit_car.S: Use tabs instead of white spaces
Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24 08:16:44 +00:00
Arthur Heymans
a28befdf8a car/non-evict/cache_as_ram.S: Use tabs instead of spaces
Change-Id: Icc5fc9ca4aadf02bd9e63b4abc02131b6c2a79da
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-21 18:16:08 +00:00
Matt DeVillier
f9aed65785 cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()
Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).

This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.

Test: build/boot each affected platform, ensure no change in functionality

Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20 22:18:05 +00:00
Elyes HAOUAS
0c0208b590 cpu: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: I67bc60b9e0eb6289193d698787c18ea4593c991a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:47:33 +00:00
Subrata Banik
53b08c347f cpuid: Add helper function for cpuid(1) functions
This patch introduces 3 helper function for cpuid(1) :

1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)

Above 3 helper functions are targeted to replace majority of cpuid(1)
references.

Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-13 04:32:57 +00:00
Nico Huber
967b1963c8 cpu/intel/fsp_model_406dx: Drop dead microcode reference
The referenced Kconfig symbols don't exist (anymore?).

Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-03 13:40:46 +00:00
Arthur Heymans
cf3076eff1 nb/intel/i945: Use common SMM_TSEG code
Use the common SMM_TSEG code to relocate the smihandler to TSEG.

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel d945gclf and Lenovo Thinkpad X60.

Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03 10:18:14 +00:00
Arthur Heymans
aaced4a932 cpu/intel/common: Use a common acpi/cpu.asl file
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
2018-11-30 22:02:35 +00:00
Arthur Heymans
cf80cda7ce cpu/intel/fsp_model_406dx: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications to the CPU.

Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29887
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30 21:52:21 +00:00
Arthur Heymans
04008a9c14 cpu/intel/model_206{5,a}x: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.

Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30 21:52:10 +00:00
Arthur Heymans
c54d14f5b4 cpu/intel/haswell: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.

Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30 21:52:00 +00:00
Arthur Heymans
8f05527485 arch/x86/acpigen.c: Add a method to notify all CPU cores
Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29 12:19:31 +00:00
Elyes HAOUAS
5ba184000b src/cpu/intel/Kconfig: Remove dead source
fsp_model_206ax was removed in Change-Id: I7b6bc4bfd

Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-11-21 12:10:19 +00:00
zaolin
3313a78e36 northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
  good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
  and NORTHBRIDGE_INTEL_SANDYBRIDGE

Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19 15:43:37 +00:00
Elyes HAOUAS
16f9bf83e0 cpu/intel/socket_mFCPGA478/Kconfig: Add MODEL_6{9,D}X
Makefile.inc uses already model_6{9,d}x subdirs.

Change-Id: I0bfc179a83fab85e5b924751e026d906d01b3fb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-19 08:13:49 +00:00
Elyes HAOUAS
55d6238fa6 src: Remove unneeded include <cbfs.h>
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:26:32 +00:00
Elyes HAOUAS
9fefd19071 src/cpu: Remove dead sourced lines
Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-15 10:25:20 +00:00
Elyes HAOUAS
d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h"
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12 09:22:18 +00:00
Tristan Corrick
fdf907e440 cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs
On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.

Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:23:21 +00:00
Tristan Corrick
ba8ead817d cpu/intel/haswell: Allow use of TSC for the monotonic timer
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.

So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.

Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:22:57 +00:00
Tristan Corrick
22f97009ad cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs
Tested on a Pentium G3258.

Change-Id: Ibf020c034c00b3bf3a7b0cda8bd3a7d40c4c13bd
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:21:44 +00:00
Elyes HAOUAS
dfbe6bd5c3 src: Add missing include <stdint.h>
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 09:41:08 +00:00
Arthur Heymans
cf2941aec2 cpu/intel/smm: Don't make assumptions on TSEG_SIZE
Do not assume:
- TSEG is 8M
- IED_REGION_SIZE is set (not needed on older platforms).

Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27872
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24 10:04:17 +00:00
Patrick Rudolph
45022ae056 intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:35:25 +00:00
Elyes HAOUAS
419bfbc1f1 src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.

Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11 21:06:53 +00:00
Elyes HAOUAS
603963e1ba src: Replace MSR addresses with macros
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-11 21:05:07 +00:00
Nico Huber
d44221f9c8 Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.

Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.

Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08 16:57:27 +00:00
Elyes HAOUAS
4e6b7907de src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-10-05 01:38:15 +00:00
Elyes HAOUAS
02820ca186 cpu/intel/car: Fix typo
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04 09:38:04 +00:00
Patrick Georgi
5b2a2d008f src/*: normalize Google copyright headers
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."

While at it, also ensure consistency in the LLC variants (exactly one
trailing period).

"Google Inc" does not need to be touched, so leave them alone.

Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-28 07:13:00 +00:00
Dan Elkouby
dfaff4d18a cpu/intel/model_206ax: detect number of MCE banks
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset
only 7. This causes Linux to spuriously log errors during boot and S3
resume.

Fix this by reading the real value from the right MSR.

Change-Id: Id05645009259fd77b4de49bde518361eeae46617
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/28443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-26 15:37:36 +00:00
Stefan Tauner
de028789fd cpu/*/car: fix ancient URL explaining XIP range run-time calculation
Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18 10:36:12 +00:00
Matt Delco
9557a34abe cpu/intel/common: add function to init cppc_config
This change adds a method to init a cppc_config structure in a way that
should ideally work across Intel processors that support EIST.

Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20 15:53:28 +00:00
Kyösti Mälkki
632b2321eb intel/socket_mPGA604: Keep only model f2x
The only board left in the tree (aopen/dxplplusu) with
this socket is the slower of the mPGA604 variants with
FSB 533.

Change-Id: I04707a0dcb8f5b6235ead8c02ddfddfe7c3b8b1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/28116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-17 12:26:36 +00:00