vboot_recovery_mode_enabled() was recently changed to assert() when it
is called before vboot logic has run, because we cannot determine
whether we're going to be in recovery mode at that point and we wanted
to flush out existing uses that pretended that we could. Turns out there
are a bunch of uses like that, and there is some code that is shared
across configurations that can and those that can't.
This patch cleans them up to either remove checks that cannot return
true, or add explicit Kconfig guards to clarify that the code is shared.
This means that using a separate recovery MRC cache is no longer
supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already
been broken with CB:38780, but with this patch those boards will boot
again using their normal MRC caches rather than just die). Skipping the
MRC cache and always regenerating from scratch in recovery mode is
likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE.
For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and
that is unlikely to change in the future so we will just hardcode that
fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed
to work around this issue).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs]
inadvertently made use of the mrc_hob conditional on
CONFIG_DISPLAY_HOBS, when there is no relation between the two,
leading to MRC cache data being corrupted. On some devices this
caused RAM training to be redone, on others it resulted in a
bricked device.
Fix this by removing the condition on CONFIG_DISPLAY_HOBS.
Test: boot google/{cyan,edgar}, observe third boot and onward do not
brick device, properly use mrc_hob via cbmem console and timestamps.
Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS.
Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs.
Use BIOS_ERR of printk() for FSP errors.
BUG=N/A
TEST=Check console output on Facebook FBG1701.
Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.
Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.
BUG=N/A
TEST=LPC Post card on Intel Cherry Hill
Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.
Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.
Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SLEEP_STATE_x definitions in the chipsets utilizing
FSP 1.1. driver have the exact same values as the ACPI_Sx
definitions. The chipsets will be moved over subsequently,
but updating this first allows the per-chipset patches
to be isolated.
BUG=chrome-os-partner:54977
Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15665
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Remove include references to the soc include directory which are not
required to build the FSP driver. Remove "duplicate" include file
definitions from file that include fsp/romstage.h. Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.
TEST=Build and run on Galileo
Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.
This will make it more consistent to debug FSP hangs and resets.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch implements Memory Margin Analysis feature in coreboot.
Few things to note
(1) the feature is enabled by setting CONFIG_MMA=y in the config file
(2) coreboot reads mma_test_metadata.bin from cbfs during romstage and
gets the name of MMA test name and test config name. Then coreboot finds
these files in CBFS.
If found, coreboot passes location and size of these files to FSP via
UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test
would be executed during memory init.
(3) FSP passes MMA results data in HOB and coreboot saves it in cbmem
(4) when system boots to OS after test is executed cbmem tool is used
to grab the MMA results data.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests
Not tested on Glados
CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479
Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7
Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299476
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12481
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
