While assembling CBFS images within the RW slots on Chrome OS
machines the current approach is to 'cbfstool copy' from the
RO CBFS to each RW CBFS. Additional fixups are required such
as removing unneeded files from the RW CBFS (e.g. verstage)
as well as removing and adding back files with the proper
arguments (FSP relocation as well as romstage XIP relocation).
This ends up leaving holes in the RW CBFS. To speed up RW
CBFS slot hashing it's beneficial to pack all non-empty files
together at the beginning of the CBFS. Therefore, provide
the 'compact' command which bubbles all the empty entries to
the end of the CBFS.
Change-Id: I8311172d71a2ccfccab384f8286cf9f21a17dec9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13479
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to more easily process the output of 'cbfstool print'
with other tools provide a -k option which spits out the
tab-separated header and fields:
Name Offset Type Metadata Size Data Size Total Size
ALIGN_UP(Offset + Total Size, 64) would be the start
of the next entry. Also, one can analzye the overhead
and offsets of each file more easily.
Example output (note: tabs aren't in here):
$ ./coreboot-builds/sharedutils/cbfstool/cbfstool test.serial.bin print
-r FW_MAIN_A -k
Performing operation on 'FW_MAIN_A' region...
Name Offset Type Metadata Size Data Size Total Size
cmos_layout.bin 0x0 cmos_layout 0x38 0x48c 0x4c4
dmic-2ch-48khz-16b.bin 0x500 raw 0x48 0xb68 0xbb0
dmic-2ch-48khz-32b.bin 0x10c0 raw 0x48 0xb68 0xbb0
nau88l25-2ch-48khz-24b.bin 0x1c80 raw 0x48 0x54 0x9c
ssm4567-render-2ch-48khz-24b.bin 0x1d40 raw 0x58 0x54 0xac
ssm4567-capture-4ch-48khz-32b.bin 0x1e00 raw 0x58 0x54 0xac
vbt.bin 0x1ec0 optionrom 0x38 0x1000 0x1038
spd.bin 0x2f00 spd 0x38 0x600 0x638
config 0x3540 raw 0x38 0x1ab7 0x1aef
revision 0x5040 raw 0x38 0x25e 0x296
font.bin 0x5300 raw 0x38 0x77f 0x7b7
vbgfx.bin 0x5ac0 raw 0x38 0x32f8 0x3330
locales 0x8e00 raw 0x28 0x2 0x2a
locale_en.bin 0x8e40 raw 0x38 0x29f6 0x2a2e
u-boot.dtb 0xb880 mrc_cache 0x38 0xff1 0x1029
(empty) 0xc8c0 null 0x64 0xadf4 0xae58
fallback/ramstage 0x17740 stage 0x38 0x15238 0x15270
(empty) 0x2c9c0 null 0x64 0xd2c4 0xd328
fallback/payload 0x39d00 payload 0x38 0x12245 0x1227d
cpu_microcode_blob.bin 0x4bf80 microcode 0x60 0x17000 0x17060
(empty) 0x63000 null 0x28 0x37cf98 0x37cfc0
Change-Id: I1c5f8c1b5f2f980033d6c954c9840299c6268431
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
VGA grub console works but display wobbles left/right
drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync
Cause: suspect single bug in raminit (chipset init)
Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove include references to the soc include directory which are not
required to build the FSP driver. Remove "duplicate" include file
definitions from file that include fsp/romstage.h. Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.
TEST=Build and run on Galileo
Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of tagging object files with .<class>, move them to a <class>
directory below $(obj)/. This way we can keep a 1:1 mapping between
source- and object-file names.
The 1:1 mapping is a prerequisite for Ada, where the compiler refuses
any other object-file name.
Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.
Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
There were several spots in the tree where the path to a per class
object file was hardcoded. To make use of the src-to-obj macro for
this, it had to be moved before the inclusion of subdirs. Which is
fine, as it doesn't have dependencies beside $(obj).
Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.
Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix GPIO config for this board:
- SD card detect to GPI
- SATA GPI to not used
- GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination
- I2C4 SDA and SCL from not used to Native
Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13431
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to
cache the MRC settings.
TEST=Build and run on Galileo
Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13437
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Intel Skylake RVP3 mainboard is not building, and according
to Intel, there is no plan to continue working on it for coreboot.
The intel/kunimitsu board is the Skylake reference design for
coreboot.org.
Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13469
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Since NetBSD does not support uname -o, push check for CygWin
inside separate non-failing condition in Makefile.
Change-Id: Ibd264384f49b33412f0ef8554bd9c9fb8f60a892
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds a check to the VPD parsing code to avoid reading the
whole thing if the first byte ('type' of the first VPD entry) is 0x00
or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types
which should never occur as the first entry, so this usually means that
the VPD FMAP section has simply never been initialized correctly. This
early abort avoids wasting time to read the whole section from SPI flash
(which we'd otherwise have to since we're not going to find a Google VPD
2.0 header either).
BRANCH=None
BUG=None
TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to
1.5ms.
Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720
Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322897
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/13467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds three timestamps to coreboot and the cbmem utility that
track the time required to read in the Chrome OS Vital Product Data
(VPD) blocks (RO and RW). It's useful to account for these like all
other large flash accesses, since their size is variable.
BRANCH=None
BUG=None
TEST=Booted Oak, found my weird 100ms gap at the start of ramstage
properly accounted for.
Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234
Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322831
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
With the introduction of flashmap cbfs alignment of files gets
broken because flashmap is located at the beginning of the flash
and cbfstool didn't take care about that offset.
This commit fixes the alignment in cbfs.
Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13417
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
What's the exact difference between TARCH, TSUPP and TBFDARCHS? Fear no
more, it's documented.
Change-Id: I18717eb1e20b1c0a82a485d391de2794a77c59ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13419
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Instead of people open coding the offset field access within a
struct buffer provide buffer_offset() so that the implementation
can change if needed without high touch in the code base.
Change-Id: I751c7145687a8529ab549d87e412b7f2d1fb90ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13468
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
gcc 4.4.7 fails to compile due to the missing initializers
for all struct members. Add initializers for all fields.
Change-Id: If1ad4fff0f965ccd7e821820c0703853c1e5c590
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13418
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of just failing with the statement:
'mv: cannot stat ‘coreboot.rom’: No such file or directory',
fail with an error that helps the user understand the issue.
Change-Id: Ie693d45710f599991514e0803a7c444636e473c9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13065
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add NetBSD-specific locations under pkg/ and missing linker flag
for libpciutils.
Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12830
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GMP's configure tries to build for 64-bit with a 32-bit userspace on
NetBSD too. Help it by forcing ABI=32.
Change-Id: I290ea0ef1626fdd88dc3ff74fadb9578ef6a1c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13067
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
