This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.
BUG=b:121212459
TEST: Verified the GPIO MISCFG is getting set as per updated map.
Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The firmware is basically ignoring F11 and F12 without this change.
BUG=b:130143385
TEST=local compile and flash to device. Confirmed that press of F11 and F12
keys now generates appropriate keypress events (and the same codes that
are already generated by these keys on an external USB keyboard).
Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing
actually active-low
BUG=b:130196983
BRANCH=none
TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff".
Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).
BUG=None
TEST=None (only documentation)
Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The value of "write protect" GPIO shall be read in depthcharge,
and the flag shall be set there instead.
BUG=b:124141368, b:124192753, chromium:1556855
TEST=Build locally
CQ-DEPEND=CL:1556855
BRANCH=none
Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The "write protect" GPIO's cached value is never actually
read after entering depthcharge. Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.
The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch. Correct some of
the values sent to boards which presumably never read the
previously incorrect value. Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.
BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.
BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.
Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This check had very few false positives which were all easily resolved,
and it's unlikely that further false positives will become problematic
in the future. On the other hand, it does detect a very severe bug (when
you think you're using a Kconfig but you aren't due to a typo), so since
warnings are currently not very visible, let's turn this into an error
because the pros clearly outweigh the cons for that.
Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Now there is no need to additionally configure the FSP
before building;
- PEG works with high link speed 8 GT/s (Gen 3);
- external GPU supported, but dynamic switching between iGPU and PEG
is not yet supported.
Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our strtol() and strtoull() function contain almost exactly the same
code. This is a) bad in general and b) may cause the code to get out of
sync, such as it recently happened with CB:32029.
This patch changes strtol() to be based on strtoull() so that the main
parsing code exists only once, and also adds a strtoll() to round off
the library. Also fix the bounds imposed by strtoul() to be based on the
actual length of a 'long', not hardcoded to 32-bits (which is not
equivalent on all architectures).
Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Our current limits.h only provides (U)INT_MAX constants. This patch adds
most others expected by POSIX. Since some of these may be different
depending on architecture (e.g. 'long' is 32-bit on x86 and 64-bit on
arm64), provide a definition that will automatically figure out the
right value for the data model the compiler is using (as long as it's
using two's complement for signed integers, which I think we can assume
these days).
Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
New compilers are a little more stringent about defining the same
prototype more than once, so some of our CONFIG_LP_DEBUG_MALLOC wrappers
don't quite work the way they are written anymore. Also, several of the
printf()s weren't written 64-bit safe. And let's add some
double-evaluation safety while I'm here anyway... and I have no idea why
this ever depended on CONFIG_LP_USB, that just seems like a typo.
Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.
BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
run 'powerinfo' in EC console and see power state in S3.
3. Wait until AP resume.
4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.
BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'
Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SMBIOS spec requires type 7 to be present.
Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.
As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity
Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.
Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
lsbpos and msbpos have incorrect behaviour when given 0.
lsbpos(0) returns 8, and msbpos(0) hangs. The latter is
because the check i >= 0 is always true for an unsigned
integer, causing it to loop indefinitely (this was flagged
by Coverity).
0 doesn't have a lsb or msb position, so we change both
functions to return -1 in this case to indicate an error.
The code already guards against calling these functions
with 0, but we make this more explicit to prevent errors
in the future.
Found-by: Coverity Scan, CID 1347356, 1347386
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.
Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.
Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The effect of pointer aliasing on writes is that any data on CPU
registers that has been resolved from (non-const and non-volatile)
memory objects has to be discarded and resolved. In other words, the
compiler assumes that a pointer that does not have an absolute value
at build-time, and is of type 'void *' or 'char *', may write over
any memory object.
Using a unique datatype for MMIO writes makes the pointer to _not_
qualify for pointer aliasing with any other objects in memory. This
avoid constantly resolving the PCI MMCONF address, which is a derived
value from a 'struct device *'.
Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
