For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables"
XSDT is primarily used to add new tables or to find the S3 resume vector.
However with QEMU coreboot does not generate most ACPI tables but takes
them from whatever QEMU provides. Qemu only creates an RSDT and lacks an
XSDT.
To keep the codebase simple with the assumption that XSDT is always
present, create an XSDT based on the existing RSDT and update the
address in RSDP.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When
creating the dpn array, the length was set to MAX - MIN or 13, numbered
0 to 12.
When accessing the array, the code was bailing out if a value greater
than MAX was trying to be accessed, so the array was able to be overrun
by two structure lengths.
Fix this problem by:
1) Not subtracting the MIN value when creating the array, which does
waste a little space. If anyone wants to refactor the code to fix that,
please feel free.
2) Breaking out of the loop when the port is equal to the MAX port
number instead of just when it's greater than the max port number.
Reported-by: Coverity (CID:1429766 & CID:1429771)
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Allow the use of 64bit MMCONF base in MCFG table.
Previously only 32 bits were utilized for MMCONF base, while the
remaining 32bits were reserved & held value of zero as evident from MCFG
table disassembly. This commit entails updating the 'base_address' field
in the 'mmconfig' structure to 64 bits and removing the 'base_reserved'
field.
TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG
table disassembly below
Signature : "MCFG"
Table Length : 0000003C
Revision : 01
Checksum : BD
Oem ID : "COREv4"
Oem Table ID : "COREBOOT"
Oem Revision : 00000000
Asl Compiler ID : "CORE"
Asl Compiler Revision : 20230628
Reserved : 0000000000000000
Base Address : 0000001010000000
Segment Group Number : 0000
Start Bus Number : 00
End Bus Number : FF
Reserved : 00000000
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.
Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.
TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.
Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.
This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
acpi.c contains architectural specific things like IOAPIC, legacy IRQ,
DMAR, HPET, ... all which require the presence of architectural headers.
Instead of littering the code with #if ENV_X86 move the functions to
different compilation units.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
With arm64 -Wstack-usage= is enabled which is triggered on any use of
alloca(). Since this function basically works on x86 without wrecking
things and causing massive stack consumption it's unlikely to cause
problems on arm64.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.
As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was missed recently when adding the table. Linux complains about
the missing checksum, e.g.
[ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173)
Tested with QEMU/Q35, albeit with changes to the special handling for
ACPI with QEMU. The warning goes away.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 90464073e4 (acpi: Add SPCR table)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sometimes systems don't boot to the OS due to wrong ACPI tables.
Printing the tables in an ACPICA compatible format makes analysis of
ACPI tables easier.
The ACPICA format (acpidump, acpixtract) is the following:
"
FACS @ 0x0000000000000000
0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$......
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
"
To achieve analyze ACPI tables capture the coreboot log between
"Printing ACPI in ACPICA compatible table" and "Done printing ACPI in
ACPICA compatible table". Remove the prefix "[SPEW ] " and then call
'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on
the .dat files to decompile the tables.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When an IO resource producer is generated that covers the whole IO space
from 0 to 0xffff, the length field in the word resource ACPI type would
overflow and be truncated which results in Linux not finding any usable
IO space to use for the PCI IO BARs. Instead generate a double word IO
resource producer to have all cases supported. Beware that covering all
IO ports with the IO resource producer while covering the PCI config IO
ports with a resource consumer in the same PCI root device will make
Linux a bit unhappy and it will complain due to the overlap, but still
end up doing the right thing:
acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored
The SoC code should make sure to carve out the PCI config IO ports from
the IO resource producer.
TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord
resource producer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very
clear that they are generating resource producer ranges and not resource
consumer ranges. To clarify this, change the function names to
acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the
ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this
doesn't change the functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Make ACPI code print a debug warning message when a timeout is
detected in a loop waiting for a condition.
This timeout message won't be displayed when this function is used as
delay loop (ie. without checking variable condition).
The following is required to get this log in kernel log buffer:
echo 1 > /sys/module/acpi/parameters/aml_debug_output
Here is an example of generated code when waiting for variable L23E to
be 0.
Local7 = 0x08
While ((Local7 > Zero))
{
If ((L23E == Zero))
{
Break
}
Sleep (0x10)
Local7--
If ((Local7 == Zero))
{
Debug = "WARN: Wait loop timeout for variable L23E"
}
}
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that the Debug print is added to the
function.
Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Generate formatted string and ACPI code to print debug string.
For example (with pcie_rp = 1):
acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp);
generates the following ACPI code:
Debug = "calling _ON for RP: 1"
With this new function, the following functions are not needed anymore
and therefore are removed by this patch.
- acpigen_concatenate_string_string()
- acpigen_concatenate_string_int()
- acpigen_write_debug_concatenate_string_string()
- acpigen_write_debug_concatenate_string_int()
BRANCH=firmware-brya-14505.B
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot. Check the debug messages is in the
kernel log when /sys/modules/acpi/parameters/aml_debug_output is
set to '1'.
Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Since it's not obvious, add comments to acpigen_resource_word,
acpigen_resource_dword and acpigen_resource_qword to clarify out what
the magic number in byte 0 means. The most significant bit of byte 0
indicates if it is a small or large resource data type. In the case of
the MSB being 0, it's a small resource data type (aka type 0), and the
other bits encode bit the type and size of the item; if the MSB is 1,
it's a large resource data type (aka type 1), and the other bits just
encode the type and there are two separate bytes to encode the size.
Beware that the large resource's data type values in the ACPI
specification don't include the MSB that's set, but only the 7 lower
bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
At present coreboot_rsdp remains unset for QEMU, which results in
an incomplete LB_TAG_ACPI_RSDP coreboot table generated.
Fix this by assigning coreboot_rsdp properly.
TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86
as the payload, boot coreboot.rom with QEMU, and run 'acpi list'
from U-Boot shell to show the ACPI tables.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
cbfs_map() can allocate memory, so cbfs_unmap() should be
called before leaving the function.
BUG=b:278264488
TEST=Built and run with additional debugs on Skyrim device
to confirm that data are correctly unmapped
Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
