7 Commits

Author	SHA1	Message	Date
Angel Pons	32abdd66a8	soc/intel/icelake: Use SPDX for GPL-2.0-only files ... Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1edbc8bb0efaad033385f29f8a4747bd178296b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>	2020-04-06 19:29:28 +00:00
Patrick Georgi	1c6d8a9cf4	soc: Remove copyright notices ... They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>	2020-03-18 16:44:46 +00:00
Kyösti Mälkki	8950cfb66f	soc/intel: Use config_of() ... Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian	2019-07-18 15:25:35 +00:00
Subrata Banik	10a9432cc2	soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer ... This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>	2019-07-11 05:57:41 +00:00
Subrata Banik	df29d23ee3	soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h ... Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-07-09 10:52:19 +00:00
Lijian Zhao	490b1d3b94	soc/intel/icelake: Fix outb order ... Similar to CB:33940, fix outb orders. Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jackpot51@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>	2019-07-06 18:23:05 +00:00
Subrata Banik	3d152ac388	soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ... As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>	2019-06-13 04:38:08 +00:00