system76-coreboot

Author SHA1 Message Date

Author	SHA1	Message	Date
Subrata Banik	3306f37fd6	lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>	2021-11-02 08:13:25 +00:00
Nikolai Vyssotski	c839b37049	soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reporting With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2021-06-30 04:47:13 +00:00
Nikolai Vyssotski	a289cdd59c	soc/amd/picasso: Move Type 17 DMI generation to common Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>	2021-06-13 09:55:30 +00:00

Subrata Banik

3306f37fd6

lib: Add new argument as ddr_type to smbios_bus_width_to_spd_width()

Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).

Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.

Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.

Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.

With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:

Handle 0x000F, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x0009
	Error Information Handle: Not Provided
	Total Width: 80 bits
	Data Width: 64 bits
	Size: 16 GB
	...

BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.

Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>

2021-11-02 08:13:25 +00:00

Nikolai Vyssotski

c839b37049

soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reporting

With two versions of *speed_mhz_to_reported_mts() we need to call the
correct one based on the reported memory type.

BUG=b:184124605
TEST="dmidecode --type 17" in OS on Guybrush

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2021-06-30 04:47:13 +00:00

Nikolai Vyssotski

a289cdd59c

soc/amd/picasso: Move Type 17 DMI generation to common

Move dmi.c code to common/fsp to be shared among different SOCs.

BUG=b:184124605

Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

2021-06-13 09:55:30 +00:00

3 Commits